Asymmetric Interconnect Structure for Parasitic Capacitance Reduction
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Solution Overview
Problem
As semiconductor industry advances, the increasing density and decreasing dimensions of integrated circuits lead to increased parasitic capacitance in back-end-of-line (BEOL) interconnect structures, necessitating improved interconnect designs to maintain electrical performance.
Innovation Solution
The implementation of partially overlapping conductive features in the interconnect structure, which reduces parasitic capacitance by optimizing the arrangement and spacing of conductive elements within the dielectric layers, thereby enhancing electrical reliability and reducing propagation delay and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between adjacent conductive features in the dielectric material is reduced to increase density, then the functionality and performance of integrated circuits improve, but parasitic capacitance effect increases
Solution Approach 1:
The patent applies asymmetry by forming conductive features with non-uniform widths along their lengths. Specifically, the conductive features have a first width at a first location and a second width at a second location, where the widths differ. This asymmetric geometry allows optimization of spacing and overlap between adjacent features, reducing parasitic capacitance while maintaining high density interconnect functionality.
2Volume of moving object
If the dimensions of conductive features are reduced to increase integration density, then more components can be packed, but new limiting factors arise that constrain further scaling
Solution Approach 1:
The patent applies local quality by varying the dimensions of conductive features at different locations along their length. The conductive features have different widths at different positions, allowing local optimization of electrical properties such as resistance and capacitance. This enables continued scaling by adjusting local geometries rather than uniformly reducing all dimensions, thereby overcoming scaling limitations.
Data Source
AI summary
An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a second conductive feature disposed over the first conductive feature. The second conductive feature includes a first sidewall, a first bottom, and a first angle between the first sidewall and the first bottom. The structure further includes a third conductive feature disposed over the dielectric layer and adjacent the second conductive feature. The third conductive feature includes a second sidewall, a second bottom, and a second angle between the second sidewall and the second bottom, the second angle is substantially different from the first angle, and the second and third conductive features are partially overlapping in an axis substantially parallel to a major surface of the substrate.