Asymmetric Interconnect Layout for Stress Migration
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Solution Overview
Problem
The miniaturization of semiconductor integrated circuits (ICs) leads to stricter design and manufacturing specifications and reliability challenges due to stress migration (SM) failure mechanisms in interconnect structures, which affect IC performance and reliability as new SM failure modes are discovered with reduced feature sizes.
Innovation Solution
The implementation of a layout design for semiconductor devices that includes specific arrangements of conductive lines and interconnect structures to reduce stress gradients and void formation, such as arranging conductive lines over or below interconnect portions with optimized widths and spacings to alleviate high-stress gradient points, thereby reducing SM failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is decreased to increase functional density, then productivity and cost are improved, but stress migration failure modes are discovered affecting reliability
Solution Approach 1:
The patent applies local quality by creating asymmetric interconnect structures where specific portions have different widths to address stress gradients locally. The first interconnect portion has a different width than the second interconnect portion, allowing targeted stress management at high-stress gradient points without affecting the entire interconnect structure uniformly.
Solution Approach 2:
The patent employs asymmetry by designing interconnect structures with non-uniform width distributions. The asymmetric layout patterns create intentional stress gradient modifications that prevent void formation at critical locations, directly addressing the reliability issue caused by stress migration in miniaturized devices.
2Adaptability or versatility
If feature size is decreased to increase functional density, then device functionality is improved, but stress gradients increase causing void formation
Solution Approach 1:
The patent addresses stress gradients locally by varying the width of specific interconnect portions rather than uniformly scaling all dimensions. This localized structural modification reduces stress gradients at critical points while maintaining the overall miniaturized functionality of the device.
Solution Approach 2:
The patent changes physical parameters of the interconnect structure, specifically the width of different interconnect portions, to modify stress distribution. By adjusting these dimensional parameters asymmetrically, the patent reduces stress gradients and prevents void formation while maintaining small feature sizes for high functionality.
3Ease of manufacture
If conventional layout design is used in miniaturized devices, then manufacturing is simplified, but new stress migration failure modes are discovered
Solution Approach 1:
The patent introduces local structural variations in the interconnect layout, creating asymmetric width patterns at specific locations. This approach maintains relative manufacturing simplicity while addressing stress migration issues that arise in miniaturized devices with conventional symmetric layouts.
Solution Approach 2:
The patent incorporates stress gradient mitigation features directly into the layout design phase, performing preliminary structural modifications before manufacturing. The asymmetric interconnect width patterns are built-in from the design stage, preventing stress migration failures before they occur rather than requiring post-manufacturing corrections.
Data Source
AI summary
A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The interconnect structure is made of conductive material and includes a first interconnect portion and a second interconnect portion. The second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion. The first conductive line is arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure. A distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end.