Asymmetric Interconnect Feature for Short-Resistant Scaling
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Solution Overview
Problem
The challenge in microelectronic device fabrication lies in forming scaled interconnect features without misalignment, which can lead to unintended electrical shorting due to technical limitations in the process, particularly with reduced pitch of interconnect features.
Innovation Solution
The approach involves creating an interconnect feature with a narrower top portion and a wider bottom portion, using techniques such as selective etching and liner layer deposition to maintain a greater lateral distance between features and reduce contact resistance, thereby minimizing the chances of electrical shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If interconnect features are scaled down with reduced pitch, then device integration density is improved, but misalignment between features increases leading to electrical shorting
Solution Approach 1:
The interconnect feature employs an asymmetric cross-sectional geometry with a narrower top portion and a wider bottom portion. This asymmetric design allows the top portion to maintain smaller dimensions for high integration density while the wider bottom portion provides a larger alignment margin to prevent electrical shorting with adjacent features, thus resolving the contradiction between scaling down for density and maintaining alignment precision for reliability.
2Productivity
If interconnect features are scaled down, then pitch is reduced improving density, but process limitations cause misalignment and electrical shorting
Solution Approach 1:
The asymmetric geometry with a narrower top and wider bottom creates a tolerance buffer zone. The wider bottom portion compensates for process-induced misalignments by providing extra lateral spacing from adjacent features, preventing electrical shorting even when scaling is pushed to its limits for high productivity.
3Quantity of substance
If interconnect features are made narrower to reduce pitch, then density increases but contact resistance increases
Solution Approach 1:
The interconnect feature exhibits local quality variation along its vertical profile: the top portion is narrower to achieve high feature density, while the bottom portion is wider to reduce contact resistance at the interface with underlying structures. This local differentiation allows simultaneous optimization of both density and electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the likelihood of electrical shorting and contact resistance, enhancing the reliability and performance of microelectronic devices by maintaining precise alignment and conductivity.
Implementation Method 1
widening a bottom portion of the recess, without correspondingly widening a top portion of the recess
Implementation Method 2
depositing a monolithic body of conductive material within the recess, to form an interconnect feature within the recess
Data Source
AI summary
An integrated circuit device includes a device layer comprising a plurality of transistor devices, and an interconnect layer above the device layer. The interconnect layer includes a conductive interconnect feature. In an example, the interconnect feature includes (i) a bottom portion having a first diameter, and (ii) a top portion above the bottom portion. In an example, the top portion has a second diameter that is less than the first diameter by at least 10%. In an example, the interconnect feature includes a monolithic body of conductive material that is within both the top portion and the bottom portion.