Asymmetric Interface Error Detection Using Concurrent Signatures
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Solution Overview
Problem
Conventional error detection methods, such as ECC and signature-based approaches, are impractical for high-speed DDR interfaces due to their inefficiency in handling multi-bit errors and the need for additional pins, which is undesirable in modern systems aiming to maintain a low pin count and high performance.
Innovation Solution
A system and method where a more intelligent controller sender/receiver computes and compares signatures with a less intelligent controlled sender/receiver for each READ or WRITE operation, using existing transmission paths to transmit signatures concurrently with data, allowing for error detection and correction without requiring additional pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC (Error Correction Code) is used for error detection and correction, then error detection capability is improved, but additional pins are required which increases device complexity and pin count
Solution Approach 1:
The patent combines the signature computation function into the memory device itself, merging the error detection capability with the existing data transmission infrastructure. The signature is computed over the data being transmitted and sent along the same interface, eliminating the need for separate error detection pins while maintaining reliability
Solution Approach 2:
The existing data interface pins are made multi-functional by using them to transmit both data and error detection signatures. The same physical pins that transmit data during normal operations are also used to transmit the computed signature, making the interface universal and eliminating additional pin requirements
2Reliability
If signature-based error detection is implemented with separate transmission paths, then error detection accuracy is improved, but processing overhead and time requirements increase
Solution Approach 1:
The signature computation and transmission occurs continuously during normal data operations rather than as a separate post-processing step. The signature is computed over the data as it is being prepared for transmission, and both data and signature are sent concurrently through the interface, eliminating idle processing time
Solution Approach 2:
The signature is computed in advance as part of the data preparation process, before the actual data transmission begins. This preliminary computation is integrated into the normal operation flow, so that when data arrives at the receiver, the signature is already ready for immediate verification, minimizing processing delays
Data Source
AI summary
A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.