Asymmetric Inverter Delay Circuit for Longer Signal Delay
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Solution Overview
Problem
Existing delay circuits require increasing the number of stages of inverters to achieve longer signal delay times, which results in increased layout area and power consumption.
Innovation Solution
A delay circuit configuration using two inverters connected in series, where the delay time of rising is larger than the delay time of falling, achieved by using P-type and N-type transistors connected in specific series configurations, allowing for reduced layout area and power consumption by using fewer transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the number of stages of inverters is increased to achieve longer signal delay times, then the signal delay time is increased, but the layout area and power consumption increase
Solution Approach 1:
The patent applies asymmetry by designing the first inverter with different transistor configurations than the second inverter. Specifically, the first inverter uses a P-type transistor and two N-type transistors while the second inverter uses two P-type transistors and an N-type transistor, creating asymmetric delay characteristics that achieve longer overall delay with fewer stages
Solution Approach 2:
The patent changes transistor parameters (width, length, type) to optimize delay characteristics. By adjusting the transistor dimensions and types in each inverter stage, the patent achieves the desired delay time with only two stages instead of requiring more traditional inverter stages
2Loss of time
If the number of stages of inverters is increased to achieve longer signal delay times, then the signal delay time is increased, but the power consumption increases
Solution Approach 1:
The asymmetric inverter design allows each stage to contribute differently to the total delay, optimizing power-delay product. The first inverter with P-type transistor and two N-type transistors provides different delay characteristics than the second inverter, achieving efficient delay accumulation with reduced power consumption
Solution Approach 2:
By optimizing transistor parameters (width, length, type) in each inverter stage, the patent achieves the target delay time with minimal power consumption. The parameter optimization ensures that each transistor operates at efficient points, reducing overall power consumption compared to traditional designs
Data Source
AI summary
A delay circuit includes a first inverter in which a delay time of rising is larger than a delay time of falling, and a second inverter which is connected in series with the first inverter and in which a delay time of falling is larger than a delay time of rising. Transistors for each of the first and second inverters are connected in series between a power supply terminal and a ground terminal.