Asymmetric Latch Module for Wide-Range Frequency Division
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Solution Overview
Problem
Existing frequency dividers face limitations in operational frequency range due to bandwidth constraints and performance at low frequencies, particularly in static frequency dividers using hetero-junction bipolar transistor technologies.
Innovation Solution
The implementation of a latch module with asymmetric current levels and a current injector to control the durations of sense and store periods, allowing for prolonged sense periods and shortened store periods without the need for multiple cascaded emitter followers, thereby enhancing high-frequency operation without penalizing low-frequency performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cascaded emitter followers are used for level shift to improve high-frequency performance, then the operational frequency increases, but the operational frequency range is reduced and low-frequency performance is penalized
Solution Approach 1:
The patent applies dynamics by making the emitter follower stage configurable through switching elements (transistors M1-M4) that can dynamically connect or disconnect the emitter followers in the signal path. This allows the circuit to adapt between different operational modes: at high frequencies the emitter followers are engaged for level shifting, while at low frequencies they can be bypassed to maintain performance across a broader frequency range.
2Speed
If asymmetric current levels are used in reading and holding paths to improve high-speed operation, then the high-frequency performance is enhanced, but the low-frequency performance is limited
Solution Approach 1:
The patent implements dynamic control of current levels through switching elements that can reconfigure the circuit topology based on operating conditions. The asymmetric current paths are enabled only when needed for high-speed operation, while the switching mechanism allows restoration of symmetric operation at lower frequencies, thus achieving adaptability across the frequency spectrum.
Solution Approach 2:
The patent changes the current level parameters dynamically by using control signals to adjust the biasing conditions and switching states of transistors. This allows the current levels in reading and holding paths to be modified according to the operating frequency, optimizing performance at different frequency ranges by adjusting the electrical parameters of the circuit.
3Speed
If different DC voltage levels are used for clock and inverted-clock signals to improve flip-flop performance at high frequencies, then the high-frequency performance is improved, but additional level shift blocks are required increasing device complexity
Solution Approach 1:
The patent merges the level shifting function with the existing clock distribution network by integrating emitter followers directly into the clock path. Instead of adding separate level shift blocks, the design combines the level shifting capability with the clock signal distribution, thereby reducing overall device complexity while maintaining high-frequency performance.
Solution Approach 2:
The emitter follower stages serve multiple functions simultaneously: they provide DC level shifting for the clock signals, acts as buffer amplifiers for signal isolation, and contribute to impedance matching. This multi-functionality eliminates the need for dedicated level shift blocks, reducing device complexity while achieving the desired high-frequency performance.
Data Source
AI summary
A latch module comprising a sense pair of transistor elements coupled together for sensing a differential input signal at input terminals, a level-shift module for producing a differential output signal at output terminals, and a regenerative pair of transistor elements coupled together and with the input pair for holding the output signal through the level-shift module. The latch module also includes a pair of gate transistor elements connected in series respectively with the sense pair of transistor elements and with the regenerative pair of transistor elements and responsive to an alternating differential gate signal to activate alternately the sense pair during sense periods and the regenerative pair during store periods. A current injector provides asymmetric operation by injecting current between at least one of the gate transistors and the corresponding sense or regenerative pair of transistor elements so that the sense periods are of different duration from the store periods.