Asymmetric LDD Driving Transistor for Organic EL Display
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Solution Overview
Problem
In organic EL display apparatuses, the parasitic capacitance between the gate and source of the driving transistor affects the bootstrap gain, leading to variations in luminance across pixels, causing vertical or horizontal stripes and irregularities, which compromise the uniformity of the display screen.
Innovation Solution
The implementation of a driving transistor with a Lightly Doped Drain (LDD) configuration, where impurity regions with lower concentration than the source/drain regions are formed between the channel region and the source/drain regions, and specifically positioned to avoid facing the gate electrode, reduces the parasitic capacitance value between the gate and source, thereby improving the bootstrap gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impurity regions are formed between the channel region and source/drain regions (LDD configuration), then the bootstrap gain is improved, but the parasitic capacitance between gate and source increases due to the additional impurity regions facing the gate electrode
Solution Approach 1:
The patent applies local quality by making the impurity region configuration asymmetric: an LDD structure is provided on the drain side to improve bootstrap gain, while the source side lacks an LDD structure to minimize parasitic capacitance. This localized differentiation allows the device to simultaneously achieve improved bootstrap gain and reduced parasitic capacitance by optimizing each region's doping structure according to its specific functional requirements.
2Reliability
If the parasitic capacitance between gate and source is reduced by positioning impurity regions to avoid facing the gate electrode, then the bootstrap gain is improved, but the manufacturing precision becomes more difficult due to the complex positioning requirements
Solution Approach 1:
The patent simplifies manufacturing by applying LDD structure only on the drain side while omitting it on the source side. This asymmetric local quality approach reduces the number of patterning and doping steps required, thereby lowering manufacturing complexity and improving yield while still achieving the dual benefits of improved bootstrap gain and reduced parasitic capacitance.
Solution Approach 2:
Instead of the conventional symmetric LDD structure on both source and drain sides, the patent inverts the approach by providing LDD only on the drain side. This inversion simplifies the manufacturing process by reducing the number of processing steps while maintaining device performance, as the source side's LDD is eliminated to reduce parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the bootstrap gain, ensuring consistent light emission luminance across pixels and maintaining high-quality display image uniformity without damaging the screen uniformity.
Implementation Method 1
the parasitic capacitance between the gate and source of the driving transistor affects the bootstrap gain
Implementation Method 2
an organic EL element which uses the phenomenon in which light is emitted when an electric field is applied to the organic thin film using electro-luminescence (EL) of an organic material
Data Source
AI summary
A display apparatus includes a plurality of pixels each including an electro-optic element, a writing transistor writing a video signal into the pixel, a holding capacitor holding the video signal written by the writing transistor, and a driving transistor driving the electro-optic element based on the video signal held in the holding capacitor. The driving transistor includes a channel region, a gate electrode disposed opposite to the channel region, a first source/drain region closer to a power source, a second source/drain region closer to the electro-optic element, and impurity regions disposed between the channel region and the first and second source/drain regions and having a lower concentration than that of the corresponding source/drain region. The impurity region disposed between the channel region and the first source/drain region is formed in a region other than a region facing the gate electrode.