Asymmetric LDD Structure for Compact High-Voltage Semiconductors
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Solution Overview
Problem
Asymmetric high-voltage semiconductor devices with a double doped drain (DDD) structure face a trade-off between increased breakdown voltage and device size, as enlarging the junction area to enhance breakdown voltage results in a larger semiconductor device.
Innovation Solution
The semiconductor device incorporates a substrate with a gate structure, source, and drain regions, featuring first and second lightly doped drain (LDD) regions with different junction depths and halo regions, along with gate spacers, to maintain breakdown voltage while reducing device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the junction area of the source region and/or drain region is increased to increase breakdown voltage, then the breakdown voltage is improved, but the overall size of the semiconductor device is increased
Solution Approach 1:
The patent applies local quality by creating asymmetric LDD regions with different doping concentrations and depths on opposite sides of the transistor. The first LDD region has a greater junction depth than the second LDD region, allowing each region to be optimized for its specific functional requirement while maintaining overall device compactness
Solution Approach 2:
The patent implements asymmetry through the DDD structure where the first LDD region and second LDD region have different characteristics (different junction depths and doping concentrations). This asymmetric design allows the device to achieve high breakdown voltage on the drain side while keeping the source side compact, thereby improving reliability without proportionally increasing overall device size
Data Source
AI summary
A semiconductor device includes a substrate, a gate structure, source and drain regions, and first and second lightly doped drain (LDD) regions. The source and drain regions are spaced apart and formed in an active region of the substrate at opposite sides of the gate structure. The first LDD region surrounds one side surface and a bottom surface of the drain region and has a first junction depth. The second LDD region surrounds one side surface and a bottom surface of the source region and has a second junction depth less than the first junction depth. The gate structure includes a gate dielectric layer, a gate electrode, and gate spacers respectively disposed on opposite side walls of the gate dielectric layer and the gate electrode. One side wall of the gate dielectric layer and electrode is aligned with one side surface of the first LDD region.