Asymmetric LDD Pixel Transistor for CMOS Image Sensor
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Solution Overview
Problem
Existing solid-state imaging apparatuses, such as CMOS image sensors, do not effectively cope with fluctuations in characteristics due to current flow direction, particularly in pixel transistors where current flows in both directions.
Innovation Solution
A solid-state imaging apparatus with a pixel array unit featuring transistors where the source-side lightly doped drain (LDD) region has a different overlap and junction depth compared to the drain-side LDD region, allowing for optimized performance across varying current flow directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional symmetric LDD structure is used in pixel transistors, then manufacturing is simpler, but characteristics fluctuate when current flows in different directions
Solution Approach 1:
The patent applies asymmetry by making the LDD structure different on the source side and drain side. Specifically, the source-side LDD has a first overlap length with the gate, while the drain-side LDD has a second overlap length that is shorter than the first. This asymmetric configuration compensates for characteristics that fluctuate depending on current flow direction, thereby improving reliability without requiring completely new device concepts.
Solution Approach 2:
The patent applies local quality by giving different properties to different regions of the transistor. The source-side LDD and drain-side LDD have different overlap lengths with the gate, creating locally optimized structures. The source-side LDD has longer overlap for better carrier injection, while the drain-side LDD has shorter overlap to reduce capacitance and improve switching characteristics, with each region tailored to its specific functional requirements.
2Productivity
If the LDD overlap length is increased to improve carrier injection, then conversion efficiency improves, but drain resistance increases
Solution Approach 1:
The patent applies local quality by optimizing the LDD structure at different locations. The source-side LDD has a longer overlap length with the gate to enhance carrier injection and improve conversion efficiency. Conversely, the drain-side LDD has a shorter overlap length to minimize drain capacitance and reduce drain resistance, thereby resolving the contradiction between conversion efficiency and drain resistance through spatially differentiated design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves photo response non-uniformity, conversion efficiency, random telegraph signal, and reduces drain resistance, effectively addressing fluctuations in characteristics depending on current flow direction.
Implementation Method 1
a pixel array unit that includes pixels having a photoelectric conversion unit
Data Source
AI summary
The present technology relates to a solid-state imaging apparatus and electronic equipment capable of coping with fluctuations in characteristics depending on the direction of current flow. There is provided a solid-state imaging apparatus including: a pixel array unit that includes pixels having a photoelectric conversion unit and arranged in a two-dimensional form, in which a transistor of the pixel has a structure in which an amount of overlap to an underside of a gate by a source-side LDD region differs from an amount of overlap to the underside of the gate by a drain-side LDD region, and a junction depth of the source-side LDD region differs from a junction depth of the drain-side LDD region. The present technology may be applied, for example, to a CMOS image sensor.