Asymmetric Log-Likelihood Ratio for Flash Memory
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Solution Overview
Problem
Multi-level cell (MLC) flash memory devices experience reduced endurance due to increased program/erase cycles, leading to reliability issues in enterprise SSD applications, as they degrade over time with stress, resulting in higher error rates during read operations.
Innovation Solution
A system and method that adjusts probability values for reading bit values from MLC flash memory cells, using a read level to differentiate between first and second binary values, and provides these adjusted probabilities to a decoder for accurate decoding, thereby reducing error rates by accounting for drift in threshold voltages over time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC flash memory is used to increase data capacity, then storage capacity is improved, but reliability deteriorates due to increased program/erase cycles and wear
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting read levels and probability values based on the age and wear state of MLC flash memory cells. The system modifies reading parameters (voltage thresholds, probability distributions) to compensate for threshold voltage drift and distribution skewness that occur over time, thereby maintaining reliable data retrieval despite increased wear from frequent program/erase cycles
2Reliability
If read levels are adjusted to account for threshold voltage drift, then error rates are reduced, but device complexity increases
Solution Approach 1:
The patent implements dynamics by making read levels and probability values adjustable rather than fixed. The system dynamically adapts reading parameters based on memory cell age, wear state, and observed error patterns. This dynamic adjustment allows the system to compensate for threshold voltage drift and distribution changes over time, reducing error rates while managing complexity through algorithmic adaptation rather than hardware complexity
Solution Approach 2:
The patent employs feedback mechanisms where the system continuously monitors read error rates and adjusts probability values and read levels accordingly. By feeding back error information and using it to refine future reading operations, the system maintains optimal performance despite changing memory conditions, effectively managing the complexity-reliability tradeoff
Data Source
AI summary
Disclosed is a system and method for reading flash memory cells with dynamically adjusted probability values (e.g., log-likelihood ratios). In connection with reading bit values from flash memory cells, one or more predetermined first probability values are adjusted relative to one or more predetermined second probability values. The one or more predetermined first probability values are associated with reading one or more memory cells programmed to a first binary value, and the one or more predetermined second probability values are associated with reading one or more memory cells programmed to a second binary value. The plurality of bit values read from the plurality of non-volatile memory cells and the one or more adjusted first probability values are provided to a decoder for use in decoding the plurality of bit values.