Asymmetric Logic Cell Structure for Critical-Path Timing
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Solution Overview
Problem
Integrated circuits (ICs) face challenges in optimizing timing performance without increasing the size or power consumption of circuit blocks, as current approaches either enhance current-driving capability by increasing cell size, leading to higher power consumption and reduced die area, or attempt to resolve timing issues by asymmetrically allocating current-driving capability among inputs.
Innovation Solution
The solution involves designing standard cells with asymmetric current-driving capabilities, where the timing-critical path is allocated more current-driving capability than non-critical paths, allowing for improved timing performance without increasing overall cell size or power consumption, achieved through the use of asymmetrical arrangements of transistor segments and pulling networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard cells with uniform dimension are used, then ease of manufacture and design convenience are improved, but timing performance on critical paths deteriorates
Solution Approach 1:
The patent applies asymmetry by allocating different current-driving capabilities to different inputs of the same standard cell. Specifically, certain inputs are assigned higher current-driving capability than others, creating an asymmetric internal structure within the otherwise uniform standard cell framework. This allows timing-critical inputs to receive stronger drive strength without changing the external cell dimensions or requiring custom cell designs.
Solution Approach 2:
The patent implements local quality by providing differentiated current-driving capability to specific inputs based on their timing requirements. Each input can be configured with appropriate drive strength locally, while the overall cell maintains uniform dimensions. This localized optimization enables timing closure on critical paths without sacrificing the manufacturing advantages of standard cells.
2Speed
If cell size is increased to improve timing performance, then signal speed is improved, but area size increases
Solution Approach 1:
The patent uses asymmetry to allocate current-driving capability unequally among inputs without increasing overall cell size. By concentrating higher drive strength on timing-critical inputs while maintaining smaller drive strength on non-critical inputs, the cell achieves improved timing performance locally without expanding the total cell area.
Solution Approach 2:
The patent changes the parameter of current-driving capability distribution rather than increasing overall cell dimensions. By adjusting the current-driving capability parameters of individual inputs asymmetrically, the patent achieves timing improvement without the area penalty that would result from uniformly scaling up cell size.
3Speed
If asymmetric current-driving capability is allocated among inputs, then timing performance is improved, but device complexity increases
Solution Approach 1:
The patent introduces controlled asymmetry in current-driving capability allocation within standard cells to improve timing performance. The asymmetry is implemented through configuration mechanisms that assign different drive strengths to different inputs based on timing requirements, rather than requiring completely custom cell designs for each timing scenario.
Solution Approach 2:
The patent achieves multi-functionality by designing standard cells that can accommodate asymmetric current-driving capability allocation. A single standard cell design can serve multiple timing scenarios by configuring different inputs with appropriate drive strengths, reducing the need for multiple specialized cell types and thereby managing device complexity.
Data Source
AI summary
A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.