Asymmetric Logic Cell Structures for Timing Optimization
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Solution Overview
Problem
Existing integrated circuit (IC) designs face challenges in optimizing performance metrics such as power consumption, area size, and signal speed at the cell level without increasing the size of the circuits or blocks along timing-critical paths.
Innovation Solution
The implementation of standard cells with asymmetric arrangements, where the current-driving capability is allocated unequally among the inputs of the cells, allows for improved timing performance without significantly changing the physical size or power consumption of the circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard cells with uniform dimension are used, then ease of manufacture and design convenience are improved, but timing performance on critical paths deteriorates
Solution Approach 1:
The patent applies asymmetry by configuring transistor segments with different widths within the same logic cell. Specifically, transistor segments associated with different inputs have different channel widths, creating unequal current-driving capabilities for different input paths. This asymmetric configuration allows timing optimization for critical paths while maintaining standard cell structural benefits for manufacturing and design convenience.
2Speed
If circuit size is increased to improve timing performance, then signal speed is improved, but area size increases
Solution Approach 1:
The patent applies local quality by differentiating transistor segment widths at specific locations within the logic cell based on their functional requirements. Transistor segments on timing-critical paths are given larger widths to improve signal speed, while non-critical paths use smaller widths. This localized differentiation optimizes timing performance without proportionally increasing the overall cell area, as the size increase is concentrated only where needed.
3Speed
If current-driving capability is increased to resolve timing issues, then signal speed is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by allocating enhanced current-driving capability (through wider transistor segments) only to specific input paths that are timing-critical. Non-critical inputs maintain their original, smaller transistor widths and thus consume less power. This selective enhancement resolves timing issues on critical paths while minimizing the overall power consumption increase of the logic cell.
Data Source
AI summary
A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.