Asymmetric Frequency-Locked Loop for Voltage-Droop Timing Margin
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Solution Overview
Problem
Integrated circuits face timing failures due to power-supply voltage variations, particularly voltage droop, which is exacerbated by increasing clock frequencies and resonance frequencies within the chip package, leading to insufficient timing margins and increased power consumption, posing design challenges in cost, complexity, and time to market.
Innovation Solution
An asymmetric frequency-locked loop (AFLL) with digitally controlled oscillators (DCOs) that select between two fundamental frequencies based on instantaneous and average power-supply voltages, adjusting the clock frequency to mitigate voltage droop effects without reducing the clock signal period, and incorporating auto-calibration to ensure stable operation across power-supply variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is increased to improve performance, then productivity is improved, but power consumption increases causing voltage droop that reduces reliability
Solution Approach 1:
The patent implements dynamic frequency adjustment by providing multiple DCOs with different fundamental frequencies and selectively activating them based on instantaneous power-supply voltage conditions. The control logic dynamically switches between DCOs to maintain stable clock operation during voltage droop events, preventing timing failures while allowing high-frequency operation during normal conditions.
Solution Approach 2:
The system changes the operating parameter (clock frequency) by selecting different DCOs with different fundamental frequencies based on power-supply voltage conditions. This parameter change allows the circuit to adapt to voltage variations, maintaining timing margins during droop events while achieving high productivity during stable operation.
2Reliability
If additional voltage margin is added to ensure proper operation during voltage droop, then reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent employs feedback by monitoring the instantaneous power-supply voltage and using this information to control which DCO is activated. The control logic continuously compares the instantaneous voltage with a reference level and adjusts the clock frequency accordingly, creating a closed-loop system that automatically maintains timing margins without requiring additional voltage headroom or complex design margins.
3Reliability
If the clock frequency is reduced during voltage droop to prevent timing failures, then reliability is improved, but productivity decreases
Solution Approach 1:
The patent segments the clock generation function into multiple DCOs with different fundamental frequencies. This segmentation allows the system to switch between different frequency modes based on power-supply conditions, maintaining high frequency (high productivity) during normal operation and switching to lower frequency (maintaining timing margins) only when voltage droop occurs, rather than operating at a consistently reduced frequency.
Data Source
AI summary
In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency that is less than the first fundamental frequency. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage so that an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced. For example, the control logic may select the first DCO if the instantaneous value of the power-supply voltage is greater than the average power-supply voltage; otherwise, the control logic may select the second DCO.