Asymmetric Mask Layer for High Aspect Ratio Trench Memory
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Solution Overview
Problem
Conventional DRAM devices face issues with electrical leakage and short circuits due to the small size of memory cells, particularly when the aspect ratio of the trench exceeds 4, leading to incomplete ion implantation and etching challenges in the fabrication process.
Innovation Solution
A method involving the formation of a trench in a substrate with a capacitor, a collar dielectric layer, and a conductive layer, where a first mask layer with a thicker bottom portion is used to reduce the aspect ratio, followed by ion implantation and selective etching to prevent complete implantation of the second mask layer, ensuring the capacitor is protected from electrical leakage and short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the aspect ratio of the trench is increased to reduce memory cell area, then the memory capacity and integration are improved, but electrical leakage and short circuit occur in the memory cell
Solution Approach 1:
The patent applies local quality by forming a thicker mask layer at the bottom portion of the trench compared to the side portions. This localized variation in mask layer thickness enables selective ion implantation - the thinner side portions allow ion penetration to modify etching characteristics, while the thicker bottom portion prevents complete implantation and protects the capacitor from electrical leakage and short circuit.
Solution Approach 2:
The patent implements preliminary action by pre-forming the asymmetric mask layer structure before ion implantation. The thicker bottom portion is prepared in advance to control the ion implantation process, ensuring that ions modify the etching characteristics of the side portions while being blocked from completely implanting into the capacitor region, thus preventing electrical leakage before the etching process occurs.
2Manufacturing precision
If ion implantation is performed to modify etching characteristics, then the manufacturing precision is improved, but complete implantation causes electrical leakage and short circuit
Solution Approach 1:
The asymmetric mask layer structure creates local quality differences that control ion implantation distribution. The thinner side portions permit ion penetration to achieve the desired etching characteristic modification for precise fabrication, while the thicker bottom portion acts as a barrier that prevents complete ion implantation into the capacitor, thereby avoiding electrical leakage and short circuit.
Solution Approach 2:
The mask layer serves as an intermediary element that mediates between the ion implantation process and the underlying structures. By designing the mask layer with varying thickness, it selectively transmits ions to modify etching characteristics where needed while blocking ions from reaching the capacitor, thus preventing electrical leakage without compromising etching precision.
3Productivity
If the memory cell size is reduced for higher integration, then the productivity and memory capacity are improved, but the trench aspect ratio increases causing fabrication difficulties
Solution Approach 1:
The asymmetric mask layer with thicker bottom and thinner sides creates local quality variations that simplify fabrication. This structure enables controlled ion implantation that modifies etching characteristics in the side portions while protecting the bottom capacitor region, making the fabrication process easier and more reliable for high-density memory cells with high aspect ratio trenches.
Solution Approach 2:
The patent changes the physical parameter of mask layer thickness distribution to optimize fabrication. By creating a thickness gradient (thicker at bottom, thinner at sides), the process parameters for ion implantation and etching are effectively controlled, enabling successful fabrication of high-aspect-ratio trenches without complete ion implantation that would cause electrical leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces electrical leakage and short circuit issues by controlling the aspect ratio of the trench and preventing ion rebound, allowing for reliable fabrication of memory devices in 0.09 μm semiconductor process technology.
Implementation Method 1
a first mask layer is formed on the conductive layer, wherein bottom portion of the first mask layer is thicker than the trench side portions
Implementation Method 2
a portion of the second mask layer in the trench is ion implanted
Implementation Method 3
The unimplanted portions of the second mask layer are removed... preventing complete implantation of the second mask layer
Data Source
AI summary
A method of manufacturing a memory device. The memory device comprises a trench in a substrate, a capacitor at the low portion of the trench, a collar dielectric layer overlying the capacitor and covering a portion of the sidewall of the trench, and a conductive layer filling a portion of the trench over the capacitor. First, a first mask layer is formed on the conductive layer, wherein a bottom portion of the first mask layer is thicker than the side portion thereof in the trench. A second mask layer is formed on the first mask layer. Next, a portion of the second mask layer in the trench is ion implanted. The unimplanted portion of the second mask layer is removed.