Asymmetric Master-Slave Data Link for Error Detection
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Solution Overview
Problem
Conventional high-speed bidirectional communication systems require complex functionality at both ends of the link, making it difficult to simplify slave devices while maintaining error detection capabilities and controlling analog properties of data waveforms.
Innovation Solution
The master device controls data transfer and performs error detection by generating and sending cyclic redundancy codes (CRC) from the slave device, allowing for asymmetric control and reducing the complexity of slave devices by calculating CRC in parallel with data transfer and adjusting signal characteristics to mitigate errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional high-speed bidirectional signaling schemes are used with symmetric control functionality at both ends, then error detection capability and control of analog properties are maintained, but slave device complexity increases
Solution Approach 1:
The patent applies asymmetry by implementing different functionality at each end of the communication link. The master device performs both transmission and reception with full error detection capability, while the slave device only performs reception. This asymmetric architecture maintains robust error detection while simplifying the slave device by removing the need for clock phase recovery, channel equalization, and error detection functions at the slave end.
Solution Approach 2:
The patent extracts the complex control functions (clock phase recovery, channel equalization, error detection) from the slave device and concentrates them in the master device. This extraction allows the slave device to be simplified to basic reception functionality while the master device retains all necessary functions for maintaining link reliability.
2Reliability
If complex control functionality is implemented at both ends of the link, then analog properties of data waveforms are controlled, but data transfer rate decreases due to processing overhead
Solution Approach 1:
The master device performs channel equalization and error detection in advance during the reception process, allowing the slave device to simply transmit data without complex processing. This preliminary action at the master end enables high data transfer rates while maintaining control over analog properties of the received signals.
3Reliability
If error detection is implemented at both ends of the link, then bit error detection capability is enhanced, but device complexity and processing overhead increase
Solution Approach 1:
The error detection function is extracted from the slave device and implemented only at the master device. The master device calculates CRC codes for received data from the slave, maintaining robust error detection capability while eliminating the processing overhead and complexity of implementing error detection at both ends of the link.
Data Source
AI summary
A system for protecting data during high-speed bidirectional communication between a master device and a slave device. The master device may control data transfer between the master device and the slave device. In addition, the master device may perform a read request to the slave device for a first data block associated with a first address and a second data block associated with a second address. In response, the slave device may send to the master device a portion of the first data block in a first burst and a portion of the second data block in a second burst via a plurality of bidirectional data paths. The slave device may further generate and send to the master device via one or more unidirectional data paths a cyclic redundancy code (CRC) based upon the first data block and the second data block.