Asymmetric Memory Access Controller for Latency Reduction
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Solution Overview
Problem
In large semiconductor integrated circuit (IC) systems, increasing memory size leads to longer access latencies due to physical routing and register breaks, resulting in degraded system performance as all memory banks are accessed with equal latency, which is inefficient and complex.
Innovation Solution
Implementing asymmetric memory access techniques by providing different access times or bandwidths for each access port to memory banks, allowing for varied access based on port and bank proximity, reducing overall average access latency without degrading performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory size is increased to accommodate larger IC systems, then memory capacity is improved, but access latency increases due to longer wire lengths and register breaks
Solution Approach 1:
The system segments memory access into multiple priority levels, dividing the access latency problem into manageable time slices. High priority accesses receive immediate attention while lower priority accesses are scheduled for subsequent time slots, effectively managing the increased latency caused by larger memory capacity without requiring physical reconfiguration of the memory structure.
Solution Approach 2:
The patent changes the temporal parameter of memory access by implementing variable latency periods for different priority levels. Instead of uniform access timing, the system dynamically adjusts access latency based on priority, allowing critical operations to bypass the delays inherent in large memory structures while maintaining overall memory capacity.
2Adaptability or versatility
If the number of bus ports and memory access ports is increased to serve more bus masters, then system versatility is improved, but access latency increases due to complex access logic
Solution Approach 1:
The patent ensures continuous memory access operations by implementing a priority-based scheduling system that eliminates idle time in the access logic. Instead of complex arbitration that causes delays, the system continuously processes memory requests by assigning priorities and executing them in sequence, maintaining high utilization of memory access ports while serving multiple bus masters.
Solution Approach 2:
The memory access system performs self-service through automated priority assignment and scheduling. The access logic automatically manages multiple bus masters without requiring complex external arbitration, with each port's requests being independently prioritized and executed based on system-defined priority levels, reducing the overhead of managing increased port complexity.
3Ease of operation
If equal access latency is provided to all memory banks, then fairness is improved, but overall system performance degrades due to maximum latency dominating the average
Solution Approach 1:
The patent introduces asymmetry into the memory access system by implementing different latency periods for different priority levels. Instead of symmetric equal-latency access to all memory banks, the system provides asymmetric treatment where high priority accesses receive shorter effective latency while lower priority accesses accept longer latency, dramatically improving overall system performance while maintaining fairness through priority-based scheduling.
Solution Approach 2:
The memory access system becomes dynamic by adjusting latency allocation based on request priority rather than maintaining static equal latency for all accesses. The system can adaptively allocate time resources to different memory banks based on current system needs, allowing critical operations to proceed faster while maintaining fairness through the priority scheduling mechanism.
Data Source
AI summary
Methods and systems are disclosed for asymmetric memory access to memory banks within integrated circuit (IC) systems. Disclosed embodiments include a memory and a memory controller within an integrated circuit. The memory includes a number of different memory banks, and the memory controller includes a number of different access ports coupled to the memory banks. The memory controller is also configured to provide asymmetric memory access for access requests to memory banks based upon access ports used for memory access requests. Additional disclosed embodiments further use asymmetric access times or asymmetric access bandwidths to provide this asymmetric access to memory banks within system memories for integrated circuit (IC) systems. By providing asymmetric access times or bandwidths for multiple access ports within a memory controller to multiple different memory banks within a system memory, overall access latency or system cost is reduced for the IC systems.