Asymmetric Memory Buffer Layout for Shorter Host C/A Traces
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Solution Overview
Problem
In computer memory systems, the long signal trace lengths from the memory controller to the registered clock driver (RCD) and then to DRAM devices lead to electrical performance issues, limiting the number of memory modules that can be connected effectively.
Innovation Solution
The memory buffer integrated circuit is positioned asymmetrically closer to the host command/address signal connections than to the memory device connections, reducing the average length of host command/address signal conductors and increasing the backside signal lengths, thereby improving electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the memory buffer integrated circuit is positioned symmetrically on the substrate, then the layout is simple and manufacturing is easier, but the host command/address signal trace length becomes too long causing electrical performance degradation
Solution Approach 1:
The patent applies asymmetry by positioning the memory buffer integrated circuit offset from the centerline of the substrate rather than in a symmetric position. Specifically, the RCD die is placed closer to the host C/A signal connections than to the memory device C/A signal connections, creating an asymmetric layout that reduces host signal trace length and improves electrical performance while maintaining manufacturability
2Quantity of substance
If more memory modules are connected to the system, then memory capacity increases, but signal quality degrades due to long trace lengths and electrical performance issues
Solution Approach 1:
The patent applies local quality by optimizing the position of the memory buffer integrated circuit to specifically address the host command/address signal path. The RCD die is strategically placed to minimize the trace length for host C/A signals while accepting longer trace lengths for memory device C/A signals, thereby locally improving signal quality where it matters most for system scalability
Data Source
AI summary
Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.