Asymmetric Memory Interconnect Buffer Phase Alignment
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Solution Overview
Problem
System memory performance in computer systems often lags behind processor speed, limiting system performance improvements, and existing solutions to enhance memory bandwidth and capacity are costly.
Innovation Solution
A memory system incorporating asymmetric high-speed differential memory interconnects, where buffer units are coupled to memory units via parallel interconnects and to a memory controller via serial interconnects, allowing for adaptive phase alignment and error detection using CRC codes, enabling efficient data transfer and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If processor speed is increased to improve system performance, then processing capability is improved, but system memory performance becomes the limiting factor
Solution Approach 1:
The memory system is segmented into multiple independent memory channels, each with its own buffer unit and serial interconnect. This allows parallel operation of multiple channels to aggregate bandwidth, effectively matching the increased processor speed without requiring proportional increases in individual memory channel performance.
Solution Approach 2:
Buffer units are introduced as intermediary components between the memory controller and memory devices. These buffer units include phase alignment circuits that act as mediators to synchronize data transfer timing, enabling higher data rates while maintaining signal integrity across the memory interconnect.
2Productivity
If memory bandwidth is increased to improve system performance, then data transfer rate is improved, but system cost increases
Solution Approach 1:
The patent replaces traditional parallel memory interconnects with serial differential interconnects. This substitution enables higher bandwidth utilization of existing physical channels while reducing the number of physical connections required, thereby lowering manufacturing costs while improving memory bandwidth.
Solution Approach 2:
The system changes the operating parameters of the memory interconnect by using differential signaling at higher data rates. This parameter change allows achieving higher effective bandwidth without proportionally increasing physical channel count or complexity, thus improving bandwidth while controlling costs.
3Ease of operation
If phase alignment is not adjusted, then data transfer simplicity is maintained, but data transfer accuracy deteriorates
Solution Approach 1:
Phase alignment circuits in the buffer units use feedback mechanisms to continuously monitor and adjust the phase of incoming data signals. This feedback-based phase adjustment ensures accurate data sampling and transfer without complicating the overall system operation, as the phase alignment is automatically maintained.
Data Source
AI summary
A memory system including asymmetric high-speed differential memory interconnect includes one or more buffer units coupled to one or more memory units such as memory modules, for example, via a parallel interconnect. The memory system also includes a memory controller coupled to each of the buffer units via a respective serial interconnect. The memory controller may control data transfer between the memory controller and the one or more buffer units. During normal operation, each of the buffer units may be configured to receive data from the memory controller via the respective serial interconnect and to transmit the data to the one or more memory units via the parallel interconnect, in response to receiving command information from the memory controller. Further, the memory controller may be configured to modify a phase alignment of information transmitted from the memory controller based upon information received from the buffer units.