Asymmetric Memory Opening Geometry for 3D NAND Density
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Solution Overview
Problem
Current three-dimensional NAND memory devices face challenges in achieving higher device density due to larger memory opening sizes and increased pitch between device elements, which limits their manufacturing efficiency and performance.
Innovation Solution
The proposed solution involves forming a three-dimensional memory device with a memory die that includes an alternating stack of insulating and electrically conductive layers, where memory openings have a greater lateral dimension at the source-side dielectric layer interface than at the drain-side dielectric layer interface, and incorporating memory opening fill structures with vertical semiconductor channels and drain regions, along with drain-select-level isolation structures to reduce pitch and enhance density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory openings are formed with conventional dimensions, then manufacturing process is simpler, but device density is lower
Solution Approach 1:
The memory openings are formed with asymmetric dimensions - specifically, the lateral dimension at the source-side dielectric layer interface is greater than at the drain-side dielectric layer interface. This asymmetric geometry allows optimized spacing and reduced pitch between device elements while maintaining manufacturability, directly increasing device density without excessive manufacturing complexity
Solution Approach 2:
The patent transitions from planar memory structures to three-dimensional vertical stacks with alternating insulating and electrically conductive layers. By utilizing the vertical dimension and creating tapered memory openings that extend through multiple layers, the design achieves higher device density while the specific asymmetric taper ratio maintains compatibility with conventional manufacturing processes
2Quantity of substance
If pitch between device elements is increased, then manufacturing is easier, but device density decreases
Solution Approach 1:
The asymmetric memory opening geometry with different lateral dimensions at source-side versus drain-side interfaces enables reduced pitch between adjacent device elements. The tapered structure optimizes space utilization, allowing closer spacing of memory openings while maintaining electrical performance and manufacturability
Solution Approach 2:
The patent implements nested structures with alternating insulating and electrically conductive layers forming vertical stacks that contain memory openings. This nested arrangement allows multiple functional layers to be integrated within a compact vertical footprint, reducing the horizontal pitch required between device elements while maintaining ease of manufacture through sequential layer deposition
3Quantity of substance
If memory opening lateral dimension is reduced, then device density increases, but manufacturing complexity increases
Solution Approach 1:
Rather than uniformly reducing memory opening dimensions, the patent employs asymmetric tapering where the lateral dimension varies systematically from source-side to drain-side. This controlled asymmetric geometry achieves density improvement through optimized spacing while maintaining a manufacturable structure that follows predictable fabrication patterns
Solution Approach 2:
The memory openings exhibit local quality variations with different lateral dimensions at different vertical levels - specifically wider at the source-side interface and narrower at the drain-side interface. This local differentiation optimizes device density and electrical characteristics while the gradual taper maintains compatibility with conventional etching and deposition processes
Data Source
AI summary
A memory die includes an alternating stack of insulating layers and electrically conductive layers located between a drain-side dielectric layer and a source-side dielectric layer. Memory openings vertically extend through the alternating stack. Each of the memory openings has a greater lateral dimension an interface with the source-side dielectric layer than at an interface with the drain-side dielectric layer. Memory opening fill structures are located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a vertical stack of memory elements, and a drain region. A logic die may be bonded to a source-side dielectric layer side of the memory die.