Asymmetric Memory Rank and ODT Configuration
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Solution Overview
Problem
Increasing the number of memory modules connected to a common transmission channel in memory systems leads to reduced data rates due to signal integrity issues and increased signal reflections, limiting the capacity without compromising data rates.
Innovation Solution
The memory system employs asymmetrically staggered memory packages and independent on-die termination (ODT) settings across different memory groups to maintain high data rates while increasing storage capacity, using a configuration of two dual inline memory modules (DIMMs) with one module having one memory rank and the other having two memory ranks, and a memory controller that generates control information for ODT settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory modules connected to a common transmission channel is increased, then storage capacity is improved, but data rate deteriorates due to signal integrity issues and increased signal reflections
Solution Approach 1:
The memory system segments the transmission channel into multiple independent channels, each serving a subset of memory modules. This segmentation reduces the number of modules sharing each channel, thereby maintaining signal integrity and data rates while achieving high aggregate storage capacity through parallel channels
Solution Approach 2:
A channel isolation mechanism acts as an intermediary between memory modules on the same channel, reducing signal reflections and interference. This intermediary function allows multiple modules to coexist on each channel without severely degrading signal integrity, enabling higher capacity per channel
2Quantity of substance
If more memory modules are connected to the same transmission channel, then system capacity is increased, but signal integrity deteriorates due to loading effects and reflections
Solution Approach 1:
Each memory module is equipped with locally adjustable termination resistors that can be independently configured based on the specific channel conditions and module position. This local quality adjustment optimizes signal matching and reduces reflections for each module-channel combination, maintaining signal integrity across high-capacity configurations
Solution Approach 2:
The termination resistor values are dynamically adjusted based on real-time channel conditions and module configurations. This dynamic adaptation allows the system to optimize signal integrity for each specific configuration, enabling reliable operation with multiple modules per channel
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances signal integrity, allowing the memory system to achieve data rates comparable to lower capacity systems, thereby increasing storage capacity without sacrificing performance.
Implementation Method 1
independent on-die termination (ODT) settings across different memory groups
Implementation Method 2
increased signal reflections, which in turn limits the data rate
Data Source
AI summary
A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks. For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. The memory controller is coupled to the memory packages of both modules via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages.