Asymmetric Memory Array Layout for Balanced RC Delays
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Solution Overview
Problem
Integrated circuits experience unbalanced signal propagation speeds and active powers due to unequal RC loads on complementary data lines caused by uneven distribution of memory cells, leading to inconsistent access speeds and power consumption during read/write operations.
Innovation Solution
Asymmetric arrangement of memory cells and complementary data lines, where one segment has fewer memory cells with shorter data lines and another segment has more memory cells with longer data lines, balancing the RC loads and reducing signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are evenly distributed across segments, then manufacturing simplicity is maintained, but RC load imbalance occurs causing unbalanced access speeds and power consumption
Solution Approach 1:
The patent applies asymmetry by configuring different numbers of memory cell arrays in different segments. Specifically, a first segment contains a first number of memory cell arrays while a second segment contains a second number of memory cell arrays, where the first number differs from the second number. This asymmetric configuration balances the RC loads on complementary data lines, achieving equalized access speeds and power consumption across the memory device despite the unequal distribution of memory cells.
2Quantity of substance
If complementary data lines are made longer to access more memory cells, then storage capacity increases, but signal delay and power consumption increase
Solution Approach 1:
The patent divides the memory device into multiple segments, where each segment contains a portion of the memory cell arrays and is served by dedicated complementary data lines. By segmenting the memory device, the data lines in each segment can be optimized independently, ensuring that no single data line becomes excessively long. This segmentation approach allows the memory device to achieve high total capacity while maintaining reasonable signal propagation delays within each segment.
Solution Approach 2:
The patent implements local quality by assigning different numbers of memory cell arrays to different segments based on their specific RC load requirements. Each segment is locally optimized to achieve balanced RC loads, with the first segment configured with a first number of memory cell arrays and the second segment configured with a second number of memory cell arrays. This local optimization ensures that each segment operates with balanced timing characteristics while the overall device achieves high capacity.
3Reliability
If RC loads on complementary data lines are made equal, then access speed balance is achieved, but memory cell distribution becomes uneven
Solution Approach 1:
The patent deliberately introduces asymmetry in the distribution of memory cell arrays across segments to achieve symmetry in RC load balance. By configuring the first segment with a first number of memory cell arrays and the second segment with a second number of memory cell arrays (where the numbers differ), the design compensates for variations in data line lengths and other parasitic effects, ultimately achieving equalized RC loads and balanced access speeds across all complementary data lines.
Data Source
AI summary
An integrated circuit includes integrated circuit includes a memory bank, a first group of word lines, a second group of word lines, an access circuit, a converter circuit and a decoder circuit. The first group of word lines is coupled to the memory bank. The second group of word lines is coupled to the memory bank, and arranged in order with the first group of word lines. The access circuit is configured to read the memory bank. The converter circuit is configured to control the access circuit at least based on a first control signal. The decoder circuit is configured to generate the first control signal at least according to a first bit and a second bit of an address signal. The first bit and the second bit indicates one group of the first group of word lines and the second group of word lines.