Asymmetric Memory Trace Spacing for Crosstalk Reduction
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Solution Overview
Problem
Traditional memory system designs with symmetric routing lead to higher maximum crosstalk, resulting in poor signal integrity and reduced performance in high-frequency circuit designs, such as LPDDR interfaces.
Innovation Solution
The implementation of an asymmetric spacing between parallel traces in memory system substrates, specifically with greater trace spacing between inner traces and reduced spacing between outer traces, to reduce capacitive and inductive coupling and thereby lower maximum crosstalk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If symmetric routing is used for parallel traces, then manufacturing simplicity and design convention are maintained, but maximum crosstalk increases and signal integrity deteriorates
Solution Approach 1:
The patent applies asymmetry by configuring parallel traces with non-uniform spacing where inner traces have greater spacing and outer traces have reduced spacing. This asymmetric arrangement reduces the maximum crosstalk between adjacent traces compared to traditional symmetric routing, directly resolving the contradiction between manufacturing simplicity and crosstalk reduction.
Solution Approach 2:
The patent implements local quality by applying different spacing criteria to different groups of traces. Inner traces receive greater spacing to reduce crosstalk in high-density regions, while outer traces have reduced spacing to optimize space utilization. This localized differentiation resolves the contradiction by optimizing each region's specific crosstalk characteristics.
2Stability of the object's composition
If symmetric routing is used for parallel traces, then design consistency is maintained, but signal integrity and eye-aperture are reduced due to higher crosstalk
Solution Approach 1:
The patent applies asymmetry by configuring parallel traces with non-uniform spacing where inner traces have greater spacing and outer traces have reduced spacing. This asymmetric arrangement reduces the maximum crosstalk between adjacent traces compared to traditional symmetric routing, directly resolving the contradiction between manufacturing simplicity and crosstalk reduction.
3Reliability
If trace spacing is increased uniformly to reduce crosstalk, then signal integrity improves, but area consumption increases and density decreases
Solution Approach 1:
The patent implements local quality by applying different spacing criteria to different groups of traces. Inner traces receive greater spacing to reduce crosstalk in high-density regions, while outer traces have reduced spacing to optimize space utilization. This localized differentiation resolves the contradiction by optimizing each region's specific crosstalk characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves signal integrity by reducing crosstalk, increasing the eye-aperture, and enabling higher data rates and operating speeds in memory systems, while maintaining the same trace width and characteristic impedance.
Implementation Method 1
reduce capacitive and inductive coupling and thereby lower maximum crosstalk
Implementation Method 2
reduce capacitive and inductive coupling and thereby lower maximum crosstalk
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
An integrated circuit is described. The integrated circuit (IC) may include a printed circuit board (PCB). The IC may also include a system on chip (SoC) die on the PCB. The IC may further include a memory device coupled to a parallel memory interface of the SoC die. The memory device may be coupled to a parallel memory interface through parallel signal traces (dmi0, dq0-dq7) arranged in an asymmetric routing. In the asymmetric routing of the parallel signal traces, the signal traces are arranged according to a variable spacing (b1>b2>b3>b4) is between the parallel signal traces for a majority portion of the parallel signal traces.