Asymmetric Sparse Mesh NoC Layout for Heterogeneous SoCs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional network-on-chip interconnects face scalability limitations and inefficiencies due to regular and structured 2D mesh topologies, which do not accommodate heterogeneous core sizes and shapes, leading to wiring congestion, timing issues, and power inefficiencies.
Innovation Solution
The development of customized sparse mesh topologies with irregular structures, synthesized from full meshes by removing routers and links, combined with static routing techniques that incorporate physical design awareness and deadlock avoidance, to optimize communication paths and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If regular 2D mesh topology is used, then routing is simple and deterministic, but it causes wiring congestion and timing issues when accommodating heterogeneous core sizes and shapes
Solution Approach 1:
The patent applies asymmetry by transitioning from a regular symmetric 2D mesh topology to an irregular asymmetric mesh topology. The asymmetric topology is generated by removing routers and links from the full mesh based on physical design constraints, allowing the network to accommodate heterogeneous core sizes and shapes without wiring congestion while maintaining routing efficiency through modified routing algorithms.
Solution Approach 2:
The patent applies local quality by allowing different regions of the mesh topology to have different properties. Specifically, certain routers and links are removed from specific locations based on physical design constraints, creating a topology where each region is optimized for its local requirements while maintaining overall network functionality.
2Adaptability or versatility
If full mesh topology is used, then all cores can be interconnected, but it increases power consumption and reduces timing closure
Solution Approach 1:
The patent applies the extraction principle by removing unnecessary routers and links from the full mesh topology. This creates a sparse mesh that maintains essential interconnection coverage while reducing the number of active components, thereby lowering power consumption and improving timing closure.
Solution Approach 2:
The patent applies partial action by implementing a sparse mesh topology that provides sufficient interconnection coverage without the excessive connectivity of a full mesh. The topology includes only the necessary routers and links required for effective communication, avoiding the power overhead of redundant connections.
3Ease of manufacture
If regular mesh topology is used, then manufacturing is standardized, but it cannot accommodate heterogeneous core sizes and shapes
Solution Approach 1:
The patent applies parameter changes by modifying the topology parameters (number of routers, number of links, connectivity patterns) to accommodate heterogeneous core sizes and shapes. The irregular mesh topology is generated by adjusting these parameters based on physical design constraints while maintaining manufacturing feasibility through systematic router and link removal.
4Use of energy by stationary object
If asymmetric sparse mesh topology is created, then power consumption is reduced and timing is improved, but routing algorithm complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing routing paths in routing tables before operation. This allows the asymmetric sparse mesh topology to handle complex routing requirements without increasing runtime algorithm complexity, as the routing decisions are made based on pre-computed tables rather than real-time calculations.
Data Source
AI summary
Example implementations described herein are directed to a system on chip (SoC) that can include a plurality of blocks of substantially non-uniform shapes and dimensions, a plurality of routers, and a plurality of links between routers. The plurality of blocks and the plurality of routers are interconnected by the plurality of links using a Network-on-Chip (NoC) architecture with a sparse mesh topology. The sparse mesh topology involves a sparsely populated mesh which is a subset of a full mesh having one or more of the plurality of routers or links removed. The plurality of blocks communicate among each other by routing messages over the remaining ones of the plurality of routers and links of the sparse mesh.