Asymmetric MOS Transistor Impurity Doping for Vd-Id Optimization
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Solution Overview
Problem
As semiconductor devices, particularly MOS transistors, shrink in size, they face challenges in achieving improved Vd-Id characteristics, requiring asymmetric transistors with specific impurity doping and structure configurations to enhance performance and efficiency.
Innovation Solution
The semiconductor device incorporates asymmetrical transistors with distinct impurity doping concentrations and depths in source/drain regions and halo regions, along with unique gate and recess structures, to improve linear components in Vd-Id characteristics compared to symmetrical transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If symmetrical transistor structure is used, then manufacturing simplicity is maintained, but Vd-Id characteristics and performance are insufficient
Solution Approach 1:
The patent applies asymmetry by forming source/drain extensions and halo regions only at one side of the gate structure rather than symmetrically at both sides. This asymmetric configuration modifies the electric field distribution and carrier transport properties, thereby improving Vd-Id characteristics while accepting increased structural complexity
Solution Approach 2:
The patent implements local quality by creating regions with different impurity concentrations and structures at specific locations. The source/drain extension and halo region are localized at one side of the gate, providing enhanced performance in critical areas without uniformly complicating the entire transistor structure
2Use of energy by moving object
If feature size is reduced, then power consumption decreases and density increases, but achieving improved Vd-Id characteristics becomes more difficult
Solution Approach 1:
The patent changes key parameters including impurity concentration gradients, source/drain extension depth, and halo region positioning to optimize Vd-_id characteristics at reduced feature sizes. By adjusting these parameters asymmetrically, the patent achieves improved performance despite smaller dimensions
Solution Approach 2:
The patent addresses feature size reduction by introducing vertical dimension variations through differently depthed source/drain extensions and halo regions. This vertical dimensionality compensation helps maintain improved Vd-Id characteristics even when horizontal feature sizes are reduced
Data Source
AI summary
Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a gate structure formed on a substrate, a source/drain extension formed at one side of the gate structure while not being formed at the other side of the gate structure, and doped with a first type impurity, a halo region formed at one side of the gate structure while not being formed at the other side of the gate structure, and doped with a second type impurity different from the first type impurity, a first source/drain region formed at one side of the gate structure and doped with the first type impurity, and a second source/drain region formed at the other side of the gate structure and doped with the first type impurity.