Asymmetric MOSFET Gate Contact Layout for Dense Transistor Packing
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Solution Overview
Problem
Current techniques for laying out integrated circuits are limited by the physical properties of metal lines, vias, and dielectric, which restrict how closely transistors can be packed due to the risk of dielectric breakdown and electrical shorts, despite advances in transistor feature sizes.
Innovation Solution
The implementation of an asymmetric gate contact over a source/drain contact in a MOSFET, with a recessed via connecting the source/drain contact to a backside power rail and a dielectric cap covering the source/drain contact, allowing for increased spacing between metal lines and vias to prevent dielectric breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor feature sizes are reduced to increase packing density, then the number of transistors per area increases, but the spacing between metal lines and vias must be reduced which increases the risk of dielectric breakdown
Solution Approach 1:
The gate contact is positioned asymmetrically to overlie the source/drain contact, utilizing the vertical dimension and lateral offset to achieve closer effective spacing while maintaining adequate dielectric clearance in the critical horizontal plane between adjacent transistor structures
Solution Approach 2:
The gate contact structure is deliberately made asymmetric relative to the source/drain contacts, with the gate contact extending over the source/drain contact region. This asymmetric configuration optimizes the spacing relationships to minimize dielectric stress while maintaining electrical functionality
2Area of stationary object
If spacing between metal lines and vias is reduced to achieve closer transistor packing, then area utilization improves, but electrical shorts between adjacent metal features may occur
Solution Approach 1:
The dielectric cap serves as an intermediary structure that covers and protects the source/drain contact region, providing additional dielectric material between the gate contact and underlying structures to prevent electrical shorts while enabling closer spacing
Solution Approach 2:
By utilizing the vertical dimension through the dielectric cap and the lateral offset positioning, the design achieves closer effective spacing without compromising electrical isolation in the critical planes where shorts would occur
Data Source
AI summary
A MOSFET includes a semiconductor substrate that has a frontside and a backside; a metal gate at the frontside of the substrate; a first source/drain structure at the frontside of the substrate, adjacent to the metal gate in a first direction; and a first source/drain contact at the frontside of the first source/drain structure. Also included are a backside power rail at the backside of the substrate; and a recessed via that connects the first source/drain contact through the substrate to the backside power rail. The recessed via is adjacent to the first source/drain structure in a direction perpendicular to the first direction. A dielectric cap covers a frontside of the first source/drain contact. A gate contact is disposed at a frontside of the dielectric cap. The gate contact at least partly overlies the first source/drain contact.