Asymmetric MOSFET Switch Configuration for Low Signal Loss
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Solution Overview
Problem
Existing transmission/reception switches using MOSFETs face challenges in achieving low loss when on and high isolation when off, particularly for high-frequency signals, as parasitic elements affect both transmission and reception systems, limiting the reduction of signal loss.
Innovation Solution
The integrated circuit and wireless communication apparatus employ a configuration with a smaller MOSFET on the transmission path and a larger MOSFET on the reception path, along with ground MOSFETs for isolation, where the second and third switch elements are turned on when the first and fourth are off, and vice versa, to minimize parasitic capacities and maintain high isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a MOSFET is used in a transmission/reception switch, then the switch can be implemented with standard semiconductor technology, but signal loss affects reception sensitivity and transmission power
Solution Approach 1:
The switch is divided into four separate MOSFETs (first, second, third, and fourth switch elements) arranged in a specific configuration. This segmentation allows independent optimization of each transistor's characteristics to minimize parasitic elements and reduce signal loss while maintaining manufacturability with standard CMOS technology.
Solution Approach 2:
Different MOSFETs in the circuit are designed with different channel widths to optimize local characteristics. The first and second MOSFETs have different channel widths, allowing each to be tailored for its specific function in the signal path, thereby reducing overall signal loss while maintaining ease of manufacture.
2Loss of energy
If the MOSFET size is increased to reduce parasitic elements, then low loss is achieved when turned on, but high isolation when turned off becomes difficult to maintain
Solution Approach 1:
The isolation function is distributed across four separate MOSFETs rather than relying on a single large transistor. This segmentation enables each MOSFET to be optimized for its specific role, achieving both low loss and high isolation through coordinated operation of multiple devices with different characteristics.
Solution Approach 2:
The four MOSFETs are designed with asymmetric characteristics, particularly in channel width, to optimize their respective functions. This asymmetry allows the circuit to achieve both low loss and high isolation by having each transistor contribute differently to the overall performance based on its specific design parameters.
3Ease of manufacture
If a single MOSFET size is used for both transmission and reception paths, then manufacturing is simplified, but loss cannot be minimized in both systems simultaneously
Solution Approach 1:
Different MOSFETs are designed with different channel widths optimized for their specific functions in the transmission and reception paths. This local quality optimization allows each transistor to minimize loss in its specific application while maintaining compatibility with standard CMOS manufacturing processes.
Data Source
AI summary
Provided is an integrated circuit including a first switch element provided on a transmission path, a second switch element provided on a reception path, a third switch element provided between an input-side node of the first switch element and a ground potential, and a fourth switch element provided between an output-side node of the second switch element and the ground potential. The second switch element and the third switch element are turned on when the first switch element and the fourth switch element are turned off. The second switch element and the third switch element are turned off when the first switch element and the fourth switch element are turned on. An output-side node of the first switch element is connected to an input-side node of the second switch element, and a size of the first switch element is smaller than a size of the second switch element.