Asymmetric MTJ Top Electrode Layout for Void-Free MRAM Interconnects

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Solution Overview

Problem

Existing MRAM devices face issues such as high chip area, high cost, high power consumption, limited sensitivity, and susceptibility to temperature variations, necessitating an improved fabrication method to address these shortcomings.

Innovation Solution

A method involving the formation of a magnetic tunneling junction (MTJ) with asymmetrical top electrodes and spacers, achieved through selective etching processes to create a planar and inclined top electrode surfaces, minimizing voids and seams in the metal interconnections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional fabrication methods are used for MRAM devices, then the device structure is simple to manufacture, but the chip area is large and power consumption is high

Engineering Contradiction:
Improvefabrication simplicityVSAvoidchip area
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent applies asymmetry by forming the top electrode with different heights on opposite sides, creating an asymmetric structure that enables more compact device layout. This asymmetric top electrode design allows for reduced chip area while maintaining fabrication feasibility through selective etching processes.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent utilizes vertical dimensionality by creating an asymmetric top electrode with varying heights, effectively using the third dimension (height) to reduce the footprint area. This dimensional approach allows the device to achieve smaller chip area without compromising manufacturing simplicity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If conventional fabrication methods are used for MRAM devices, then the manufacturing process is straightforward, but power consumption is high

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidpower consumption
Core Design Contradiction:
Ease of manufactureVSUse of energy by stationary object

Solution Approach 1:

The asymmetric top electrode structure with different heights on opposite sides reduces the overall device volume and capacitance, leading to lower power consumption while maintaining a straightforward manufacturing process based on selective etching and standard deposition techniques.

Inventive Principle:
Principle #4Asymmetry

3Ease of manufacture

If conventional fabrication methods are used for MRAM devices, then the device structure is conventional, but sensitivity is limited

Engineering Contradiction:
Improveconventional structureVSAvoidsensitivity
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The asymmetric top electrode structure enhances sensitivity by creating an asymmetric magnetic field distribution that improves the magnetoresistive effect detection capability, while still utilizing conventional fabrication techniques.

Inventive Principle:
Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enhances device performance by reducing chip area, lowering power consumption, and improving sensitivity while being less affected by temperature variations.

Implementation Method 1

Magnetoresistance (MR) effect has been known as a kind of effect caused by altering the resistance of a material through variation of outside magnetic field

Methodology Applied
Scientific EffectMagnetic tunneling effect: Magnetoresistance

Data Source

PatentUS12501835B2Semiconductor device and method for fabricating the same
Publication Date: 2025.12.16 UNITED MICROELECTRONICS CORP
  • US12501835B2 patent drawing
  • US12501835B2 patent drawing
  • US12501835B2 patent drawing

AI summary

A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate and a top electrode on the MTJ; forming a first inter-metal dielectric (IMD) layer around the MTJ and the top electrode; forming a stop layer on the first IMD layer; forming a second IMD layer on the stop layer; performing a first etching process to remove the second IMD layer and the stop layer; performing a second etching process to remove part of the top electrode; and forming a metal interconnection to connect to the top electrode.