Asymmetric Multi-Core Shared Memory Manager

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Solution Overview

Problem

Traditional multi-core operating systems face inefficiencies due to duplication of hardware components, lack of communication and task sharing between cores, and high power consumption, leading to redundancy and interference in managing kernel services for mobile devices.

Innovation Solution

Implementing an asymmetric multi-core structure with a shared memory manager and scheduler, allowing threads to be offloaded from a primary core to secondary cores for execution, which reduces power consumption and eliminates redundant address translations by using cores with varying speeds and capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If each core has its own dedicated memory manager and scheduler, then each core can independently manage kernel services, but hardware components are duplicated leading to redundancy and increased complexity

Engineering Contradiction:
Improveindependent core managementVSAvoidhardware duplication
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a shared memory manager that serves multiple cores, eliminating the need for each core to have its own dedicated memory manager. This merging approach reduces hardware redundancy while maintaining the ability of each core to independently manage kernel services through the shared resource.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared memory manager serves multiple functions by providing memory management services to multiple different cores, making it a universal component rather than core-specific. This multi-functionality reduces the overall hardware footprint while maintaining system reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Ease of operation

If cores operate at the same speed, then scheduling is simplified, but power consumption increases when all cores must run at high performance

Engineering Contradiction:
Improvescheduling simplicityVSAvoidpower consumption
Core Design Contradiction:
Ease of operationVSUse of energy by moving object

Solution Approach 1:

The patent implements asymmetric core architecture where different cores operate at different speeds based on their specific workload requirements. This allows each core to have optimized local performance characteristics rather than uniform system-wide performance, enabling power savings on cores that don't require maximum speed.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system dynamically adjusts core operating speeds based on actual task requirements rather than maintaining fixed uniform speed. This dynamic adaptation allows the system to optimize the balance between scheduling complexity and power consumption by matching core performance to actual needs.

Inventive Principle:
Principle #15Dynamics

3Productivity

If threads are executed on multiple cores, then task processing capacity increases, but context switching overhead and interference between cores increase

Engineering Contradiction:
Improvetask processing capacityVSAvoidcontext switching overhead
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The shared memory manager acts as an intermediary between multiple cores and the memory subsystem, centralizing memory management decisions and reducing direct interference between cores. This mediator approach allows threads to be distributed across multiple cores for increased productivity while the shared manager handles context switching coordination.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Adaptability or versatility

If all cores are used for kernel services, then service coverage is maximized, but power consumption increases due to multiple high-speed cores

Engineering Contradiction:
Improveservice coverageVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

Different cores are assigned different operational characteristics based on their roles - some cores operate at higher speeds for performance-critical kernel services while others operate at lower speeds for less demanding tasks. This local quality differentiation maintains comprehensive service coverage while optimizing overall power consumption.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8566832B1Power optimization for multi-core devices having a shared memory manager
Publication Date: 2013.10.22 MARVELL ASIA PTE LTD
  • US8566832B1 patent drawing
  • US8566832B1 patent drawing
  • US8566832B1 patent drawing

AI summary

Methods and systems for a multi-core processing system are described. In one embodiment, an apparatus comprises a first operating system (OS) core for managing kernel services. The first OS core includes a first physical memory, a first memory manager, and a first scheduler for scheduling a process to be executed, wherein the process is associated with a plurality of threads. At least two second OS cores comprise a second OS core and a third OS core. The apparatus includes a shared memory manager and a shared scheduler that are shared by the at least two second OS cores. The shared memory manager and the shared scheduler are configured to communicate with the first memory manager and the first scheduler, respectively, to initiate offloading of one or more of the threads from the first OS core to at least one of the at least two second OS cores for execution.