Asymmetric Multicore Architecture Same Instruction Set Power Management

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Solution Overview

Problem

Existing multi-core processors with identical cores face challenges in power management, as reducing processing performance to save power is not efficiently scalable, and switching between cores with different instruction sets is difficult, leading to suboptimal power consumption and performance.

Innovation Solution

Designing a multi-core processor with both high and low power cores that share the same instruction set architecture, where low power cores have narrower drive transistor widths and opposite power consumption design features, allowing for dynamic power management without software adjustments, enabling lower power consumption while maintaining performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multi-core processors use identical cores with same instruction set architecture, then software compatibility is maintained, but power management efficiency deteriorates due to inability to dynamically switch between performance modes

Engineering Contradiction:
Improvesoftware compatibilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent applies local quality by creating processor cores with different power consumption characteristics while maintaining the same instruction set architecture. Specifically, it uses different transistor width configurations in different cores - narrower transistors in low-power cores and wider transistors in high-performance cores - allowing the system to locally optimize power consumption based on workload requirements without sacrificing software compatibility.

Inventive Principle:
Principle #3Local quality

2Use of energy by moving object

If processor cores have different power consumption characteristics, then power management efficiency improves, but system complexity increases due to heterogeneous core designs

Engineering Contradiction:
Improvepower consumptionVSAvoidcore design heterogeneity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by modifying physical parameters of the processor cores - specifically transistor widths and other hardware parameters - to create different power consumption characteristics. By changing these physical parameters rather than creating fundamentally different architectural designs, the system achieves power management efficiency while limiting the increase in system complexity.

Inventive Principle:
Principle #35Parameter changes

3Use of energy by moving object

If dynamic power management is implemented with different core types, then energy efficiency improves, but software transparency deteriorates requiring special adjustments

Engineering Contradiction:
Improveenergy efficiencyVSAvoidsoftware transparency
Core Design Contradiction:
Use of energy by moving objectVSEase of operation

Solution Approach 1:

The patent applies universality by ensuring all processor cores, regardless of their power consumption characteristics, support the same instruction set architecture. This multi-functionality allows software to operate transparently across different core types without requiring special adjustments or awareness of the underlying hardware heterogeneity, while still enabling dynamic power management through workload-based core selection.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10740281B2Asymmetric performance multicore architecture with same instruction set architecture
Publication Date: 2020.08.11 DAEDALUS PRIME LLC
  • US10740281B2 patent drawing
  • US10740281B2 patent drawing
  • US10740281B2 patent drawing

AI summary

A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.