Asymmetric N-P Transistor Memory Cell for Power Efficiency
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Solution Overview
Problem
Nonvolatile memory systems face challenges in improving power efficiency and dielectric breakdown resistance due to increased drain-to-source current and power consumption when widening the gate width or reducing the gate length of MOS transistors to meet threshold current requirements for source-to-drain current.
Innovation Solution
Incorporating both N-type and P-type transistors with different gate widths and lengths, where the N-type transistor has a narrower gate width and longer gate length than the P-type transistor, to manage current direction and reduce unnecessary drain-to-source current, thereby enhancing memory cell performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate width of the MOS transistor is widened or the gate length is reduced to increase the source-to-drain current I1, then the source-to-drain current I1 becomes equal to or larger than the threshold current, but the drain-to-source current I0 becomes larger than necessary, causing increased power consumption and dielectric breakdown risk
Solution Approach 1:
The patent divides the single transistor into two separate transistors: an N-type transistor for supplying source-to-drain current and a P-type transistor for supplying drain-to-source current. This segmentation allows independent optimization of each transistor's gate dimensions, enabling the N-type transistor to have sufficient current drive capability while the P-type transistor maintains lower current to reduce power consumption and prevent dielectric breakdown.
Solution Approach 2:
The patent applies different gate width-to-length ratios to the N-type and P-type transistors based on their specific functional requirements. The N-type transistor uses a larger gate width-to-length ratio to ensure sufficient source-to-drain current, while the P-type transistor uses a smaller gate width-to-length ratio to limit drain-to-source current, achieving local optimization of current characteristics.
2Productivity
If the gate width is widened or the gate length is reduced to make the source-to-drain current I1 equal to or larger than the threshold value, then the rewriting capability is improved, but the drain-to-source current I0 becomes excessively large, causing dielectric breakdown or increased power consumption
Solution Approach 1:
The patent segments the current supply function into two independent transistors with different current characteristics. The N-type transistor is optimized for high source-to-drain current to enable reliable data rewriting, while the P-type transistor is optimized for lower drain-to-source current to prevent dielectric breakdown, thus resolving the contradiction between rewriting capability and dielectric safety.
Solution Approach 2:
The patent changes the electrical parameters (gate width and gate length) of the two transistors differently to achieve distinct current characteristics. By setting the N-type transistor with a larger gate width-to-length ratio and the P-type transistor with a smaller gate width-to-length ratio, the patent creates asymmetric current profiles that simultaneously enable effective rewriting and prevent dielectric breakdown.
Data Source
AI summary
An object of the present technology is to improve the performance of a memory cell that stores the value reflecting the direction of an electric current. The memory cell includes an N-type transistor, a P-type transistor, and a storage element. The N-type transistor supplies a current either from a source to a drain thereof or from the drain to the source. The P-type transistor supplies a current from a source to a drain thereof. The storage element stores a logical value reflecting the direction of the current supplied from the drain of the N-type transistor and from the drain of the P-type transistor.