Asymmetric Overlapping NAND Die Stacks Beyond Shingled Overhang Limits

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Solution Overview

Problem

The existing shingled stacking approach for semiconductor dies is limited by the increasing overhang of each additional die, which restricts the number of dies that can be stacked and increases manufacturing complexity and costs due to multiple stacking and wirebonding operations.

Innovation Solution

The implementation of overlapping die stacks with asymmetric heights, where one stack is taller than the other, allowing for a greater overlap and reducing the surface area occupied on the substrate, thereby enabling a higher density of dies without the need for multiple stacking and wirebonding operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If shingled stacking approach is used to increase die capacity, then the number of dies that can be stacked increases, but the overhang of each additional die increases and manufacturing complexity increases

Engineering Contradiction:
Improvenumber of dies stackedVSAvoidmanufacturing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent employs asymmetric stacking where a first stack of dies has a different height than a second stack of dies. This asymmetry allows the stacks to be positioned at different locations on the substrate without requiring uniform overhang compensation, thereby reducing manufacturing complexity while maintaining high die density. The asymmetric configuration enables simpler wirebonding operations compared to symmetric shingled stacking.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent transitions from two-dimensional shingled stacking (where dies are offset laterally) to a three-dimensional overlapping configuration where stacks of different heights are positioned vertically and horizontally. This dimensional change allows dies to be stacked more densely without the cumulative overhang problem inherent in traditional shingled approaches, reducing both manufacturing complexity and substrate area requirements.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If shingled stacking approach is used to increase die capacity, then the number of dies that can be stacked increases, but multiple stacking and wirebonding operations are required

Engineering Contradiction:
Improvenumber of dies stackedVSAvoidmanufacturing efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent merges multiple stacking operations into a simplified process by creating stacks of different heights that can be positioned and connected more efficiently. The asymmetric stacking allows for consolidated wirebonding operations compared to traditional shingled stacking, where each die required separate bonding. This merging of operations improves manufacturing efficiency while achieving high die capacity.

Inventive Principle:
Principle #5Merging (Combining)

3Area of moving object

If overlapping die stacks with asymmetric heights are used, then surface area occupied is reduced and die density increases, but stack height difference must be controlled

Engineering Contradiction:
Improvesurface area occupiedVSAvoidstack height control
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

The patent applies local quality by allowing different regions of the substrate to have different stack heights tailored to specific functional requirements. Rather than enforcing uniform height control across the entire device, the asymmetric stacking enables localized height variations that optimize die density in certain areas while maintaining manufacturability. This localized approach reduces the overall manufacturing precision requirements compared to uniform height constraints.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11908833B2Overlapping die stacks for nand package architecture
Publication Date: 2024.02.20 MICRON TECHNOLOGY INC
  • US11908833B2 patent drawing
  • US11908833B2 patent drawing
  • US11908833B2 patent drawing

AI summary

A semiconductor device assembly includes a substrate, a first stack of semiconductor dies disposed directly over a first location on the substrate, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.