Asymmetric Bonding Pad Assembly for Stronger Void-Resistant Die Bonding
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Solution Overview
Problem
Existing semiconductor bonding technologies face challenges in achieving enhanced bonding strength due to limitations in bonding pad size and density, which can lead to CMP-induced post-bonding void formation and processing issues.
Innovation Solution
A bonded assembly is formed using semiconductor dies with primary and complementary bonding pads of different sizes, where the larger pads are bonded to smaller pads, reducing local bonding pad density and minimizing void formation through hybrid bonding that combines dielectric-to-dielectric and metal-to-metal bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If bonding pad size is increased to enhance bonding strength, then bonding strength is improved, but local bonding pad density increases leading to CMP-induced void formation
Solution Approach 1:
The patent implements a heterogeneous bonding pad configuration where different regions of the bonding interface have different pad sizes. Specifically, first bonding pads on the primary die are paired with second bonding pads on the complementary die that have different dimensions, creating local variations in pad density. This local quality differentiation allows certain regions to have larger pads for enhanced bonding strength while other regions have smaller pads that maintain lower local density, thereby preventing CMP-induced void formation while achieving overall strong bonding.
2Strength
If uniform bonding pad size is used, then manufacturing simplicity is maintained, but bonding strength is limited due to inability to optimize for different bonding requirements
Solution Approach 1:
The patent employs asymmetric bonding pad pairing where the first bonding pads and second bonding pads differ in size and dimensions. This asymmetry is deliberately introduced to optimize bonding performance - larger pads provide enhanced bonding strength and larger bonding area, while the asymmetric configuration prevents uniform high density that causes CMP voids. The asymmetric design is implemented through separate patterning processes for each die, allowing independent optimization of pad dimensions on the primary and complementary dies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances bonding strength and reduces CMP-induced voids by optimizing bonding pad size and density, allowing for more efficient semiconductor die bonding while maintaining a low maximum local copper bonding pad area density.
Implementation Method 1
Metal-to-metal bonding may be employed to provide signal paths between the pair of semiconductor dies
Implementation Method 2
hybrid bonding that combines dielectric-to-dielectric and metal-to-metal bonding
Data Source
AI summary
A bonded assembly of a primary semiconductor die and a complementary semiconductor die includes first pairs of first primary bonding pads and first complementary bonding pads that are larger in area than the first primary bonding pads, and second pairs of second primary bonding pads and second complementary bonding pads that are smaller in area than the second primary bonding pads.