Asymmetric Bonding Pad Layout for Die Stack Bond Testing

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current semiconductor die stacking technologies face challenges in efficiently testing and bonding semiconductor dies with asymmetrical bonding pad arrays, leading to complexities in electrical connectivity and error detection during the bonding process.

Innovation Solution

The implementation of a semiconductor die stack configuration where upper and lower semiconductor dies are bonded in a face-to-face form with specific asymmetrical bonding pad arrangements, allowing for direct vertical alignment and bonding of certain pads while others remain electrically connected to specific circuits, enabling simultaneous testing and error detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If asymmetrical bonding pad arrays are used in semiconductor dies, then bonding flexibility and electrical circuit design are improved, but testing complexity and error detection difficulty increase

Engineering Contradiction:

Improvebonding flexibilityVSAvoiderror detection difficulty

Core Design Contradiction:

Adaptability or versatilityVSDifficulty of detecting and measuring

Solution Approach 1:

A dedicated test bonding pad is introduced as an intermediary element that is not connected to any electrical circuit in either the first or second semiconductor die. This test pad serves as a mediator to establish a known good bonding path, enabling independent verification of bonding quality without interference from circuit functionality. The test pad acts as a reference point that simplifies error detection by providing a baseline for comparison.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The bonding pad array is segmented into functionally distinct groups: circuit-connected bonding pads that participate in electrical operations, and dedicated test bonding pads that are isolated from circuits. This segmentation allows independent testing of bonding quality separate from circuit functionality, enabling targeted error detection and analysis without the complexity of integrated circuit testing.

Inventive Principle:

Principle #1Segmentation

2Reliability

If dedicated test bonding pads are added, then bonding error detection capability is improved, but device complexity and manufacturing steps increase

Engineering Contradiction:

Improvebonding error detection capabilityVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The dedicated test bonding pads serve multiple functions: they act as reference points for bonding alignment, provide test signals for verifying bonding integrity, and enable independent error detection without requiring separate testing equipment or procedures. This multi-functionality reduces the need for additional complex testing infrastructure, offsetting the added device complexity with operational efficiency.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

Rather than implementing complex testing mechanisms across the entire device, the solution applies local quality enhancement by placing simple, dedicated test bonding pads at specific locations. These localized test elements provide targeted error detection capability without requiring complex testing architecture throughout the entire semiconductor device, thus minimizing the increase in overall device complexity.

Inventive Principle:

Principle #3Local quality

3Manufacturing precision

If asymmetrical bonding pad configuration is implemented, then bonding alignment precision is improved, but manufacturing process complexity increases

Engineering Contradiction:

Improvebonding alignment precisionVSAvoidmanufacturing process complexity

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The asymmetrical bonding pad configuration, including the placement of dedicated test bonding pads, is predetermined and pre-configured during the semiconductor fabrication process. This preliminary action establishes precise alignment references before bonding occurs, enabling accurate alignment during the bonding step without requiring complex real-time adjustment mechanisms, thus improving precision while managing manufacturing complexity.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20240071967A1Semiconductor die including an asymmetric pad arrays, a semiconductor die stack including the semiconductor die, and a high bandwidth memory including the semiconductor die stack

Publication Date: 2024.02.29 SK HYNIX INC

AI summary

A semiconductor die stack includes a lower semiconductor die and an upper semiconductor die. The upper semiconductor die includes a first upper bonding pad disposed in a first upper bonding pad region; and a second upper bonding pad disposed in a second upper bonding pad region. The lower semiconductor die includes a first lower bonding pad disposed in a first lower bonding pad region; and a second lower bonding pad disposed in a second lower bonding pad region. The second upper bonding pad and the first lower bonding pad are vertically aligned and directly bonded to each other. The second upper bonding pad and the first lower bonding pad are not electrically connected to an upper electrical circuit in the upper semiconductor die, and electrically connected to a lower electrical circuit in the lower semiconductor die.