Asymmetric Hybrid Bonding Pads for Misalignment-Tolerant 3D Memory
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Solution Overview
Problem
Current semiconductor devices face challenges in maximizing data storage capacity and electrical characteristics due to limitations in pad design and alignment during fabrication, leading to potential misalignment and increased contact resistance.
Innovation Solution
The semiconductor device incorporates a unique pad structure with alternating larger and smaller pads on each substrate, ensuring uniform contact and reduced contact resistance, even in cases of misalignment, by using intermetallic hybrid bonding and specific pad configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional pad alignment methods are used during fabrication, then manufacturing process simplicity is maintained, but misalignment occurs leading to increased contact resistance
Solution Approach 1:
The patent employs asymmetric pad design where bonding pads on the first substrate have different dimensions than corresponding pads on the second substrate. Specifically, the first bonding pads have a first dimension while the second bonding pads have a second dimension that is different from the first dimension. This asymmetric configuration creates a tolerance buffer that accommodates alignment variations during fabrication, thereby reducing contact resistance without requiring extremely precise alignment.
Solution Approach 2:
The asymmetric pad design serves as a pre-built cushioning mechanism against potential misalignment. By designing pads with intentionally different dimensions before the bonding process, the structure anticipates and compensates for alignment variations that may occur during fabrication, ensuring reliable electrical contact without needing post-fabrication adjustment.
2Reliability
If larger bonding pads are used to reduce contact resistance, then electrical characteristics improve, but device area increases reducing data storage capacity
Solution Approach 1:
The patent applies local quality by making bonding pads asymmetric in size rather than uniformly large. The first bonding pads and second bonding pads have different dimensions, allowing each pad to be optimized for its specific function and location. This enables sufficient contact area for low resistance where needed, while minimizing total pad area to preserve data storage capacity in other regions of the device.
Solution Approach 2:
Instead of making all bonding pads uniformly large (excessive action), the patent uses partial action by making only certain pads larger while others are smaller. This selective approach provides sufficient bonding area for reliable electrical contact without unnecessarily increasing the total device area, thus maintaining data storage capacity.
3Ease of manufacture
If misalignment is tolerated in pad bonding, then fabrication complexity is reduced, but short-circuits may occur between adjacent pads
Solution Approach 1:
The asymmetric pad configuration creates distinct size differences between first and second bonding pads, which serves as a built-in alignment guide. This size differentiation helps prevent adjacent pads from overlapping or short-circuiting even when some misalignment occurs during bonding, as the larger pads provide a margin of error that prevents contact between adjacent structures.
Solution Approach 2:
The design incorporates a cushioning effect by making certain pads larger than others before the bonding process. This pre-built dimensional buffer zone prevents short-circuits between adjacent pads even when misalignment occurs, as the larger pads create sufficient spacing that accommodates fabrication tolerances without causing electrical shorts.
Data Source
AI summary
A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.