Asymmetric Partial Link Width States for Bidirectional Multilane Links
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Solution Overview
Problem
Current interconnect architectures in computing systems face challenges in achieving optimal power savings while maintaining high performance, particularly in scenarios where bandwidth demand is asymmetric, as they often result in increased latency and Quality of Service (QoS) issues due to traditional dynamic link width adjustment mechanisms.
Innovation Solution
The implementation of asymmetric partial link width states allows for dynamic power allocation by keeping the link active during reconfiguration, enabling power consumption to be proportional to bandwidth usage without causing link downtime, through mechanisms like partial L0 (PL0) states and retimer-based sub-links, which facilitate seamless merging of active and inactive lanes during link width adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional dynamic link width adjustment mechanisms are used to save power, then power consumption is reduced, but latency increases and QoS deteriorates
Solution Approach 1:
The patent implements dynamic link width adjustment where the interconnect link can transition between different operational states (full width, partial width, and asymmetric states) based on real-time bandwidth demands. This allows the system to optimize power consumption by reducing link width during low-utilization periods while maintaining full performance when needed, thereby resolving the contradiction between power savings and latency.
Solution Approach 2:
The system changes the operational parameters of the interconnect link by adjusting link width and introducing asymmetric states where upstream and downstream directions can have different widths. This parameter adjustment enables power-efficient operation during asymmetric bandwidth scenarios without causing full link shutdown, thus reducing latency while saving power.
2Use of energy by stationary object
If traditional dynamic link width adjustment mechanisms are used to allocate power dynamically, then power management is improved, but QoS deteriorates due to link downtime
Solution Approach 1:
The patent segments the interconnect link into independent directional channels (upstream and downstream) that can be adjusted independently. This segmentation allows the system to maintain QoS in critical directions while reducing power consumption in less utilized directions, avoiding complete link shutdown and preserving service reliability.
Solution Approach 2:
The system introduces asymmetric link width states where the upstream and downstream directions can have different operational widths simultaneously. This asymmetry enables optimized power management tailored to actual bandwidth patterns in each direction, maintaining QoS where needed while reducing power consumption where bandwidth demand is lower, thus avoiding the QoS deterioration caused by traditional symmetric link shutdown approaches.
3Productivity
If full link width is maintained to ensure high performance, then bandwidth is maximized, but power consumption increases
Solution Approach 1:
The patent implements partial link width operation where only the necessary number of lanes are activated based on actual bandwidth demands. Instead of maintaining full link width continuously, the system activates only the required portion (e.g., 4x or 8x width instead of 16x), achieving sufficient bandwidth for current workloads while significantly reducing power consumption. The link can be dynamically scaled up or down as demands change.
Data Source
AI summary
A system can include a host device that includes a downstream port and an endpoint device that includes an upstream port. A bidirectional multilane link can interconnect the downstream port and the upstream port. The downstream port can send a request to the upstream port across the bidirectional multilane link to change a number of active lanes in a first direction on the bidirectional multilane link, the request comprising an indication of a desired link width, receive an acknowledgment from the upstream port to change the number of active lanes on the bidirectional multilane link to the desired link width in the first direction, configure the bidirectional multilane link to operate using the desired link width, and send or receiving data to the upstream port using the desired link width. The change in link width can be asymmetrical (i.e., the upstream link width is different from the downstream link width).