Asymmetric PCB Via Layout for Crosstalk and Current Capacity
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Solution Overview
Problem
The increasing bandwidth requirements and pin density in integrated circuit chips lead to denser vias with smaller diameters, causing crosstalk issues, increased PCB thickness, and manufacturing difficulties, affecting signal integrity and current capacity.
Innovation Solution
A printed circuit board design with asymmetric layered structure, featuring smaller diameter signal vias and power vias, and capacitive load pads to mitigate crosstalk and inductive load, along with a manufacturing method that separates and overlays signal and power plane portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of signal pins and power pins increases to meet bandwidth requirements, then the signal transmission capability is improved, but the pin spacing decreases and via density increases, leading to manufacturing difficulty and reduced yield
Solution Approach 1:
The patent divides the via structure into two distinct types: signal vias with smaller diameters optimized for high-density signal routing, and power vias with larger diameters optimized for current carrying capacity. This segmentation allows each via type to be independently optimized for its specific function, resolving the conflict between high pin density and manufacturing feasibility
Solution Approach 2:
The patent applies different via diameter specifications at different locations and for different functions: smaller diameters for signal vias in high-density regions, and larger diameters for power vias in current-carrying regions. This local differentiation of via quality parameters enables the PCB to accommodate both high pin count and manufacturable via dimensions
2Quantity of substance
If via diameter is reduced to increase via density, then the pin density capability is improved, but the inductive load of via increases causing signal reflection and degraded signal integrity
Solution Approach 1:
The patent segments via functions by creating dedicated signal vias with smaller diameters for high-frequency signal routing and separate power vias with larger diameters for power delivery. The smaller signal via diameters are optimized to reduce inductive effects and minimize signal reflection, while maintaining high via density for signal pins
Solution Approach 2:
The patent changes the diameter parameter of vias based on their function: smaller diameters (e.g., 0.15-0.25mm) for signal vias to reduce inductance and signal reflection, and larger diameters (e.g., 0.3-0.5mm) for power vias to reduce resistance and improve current carrying capacity. This parameter optimization resolves the conflict between via density and signal integrity
3Quantity of substance
If the number of power planes is increased to ensure current capability, then the current capacity is improved, but the PCB thickness increases, further increasing via aspect ratio and manufacturing difficulty
Solution Approach 1:
The patent segments power delivery into two via types: power vias that extend through the entire PCB thickness to reach distant power planes, and signal vias that terminate before reaching power planes. By using larger diameter power vias for through-board power delivery, the patent reduces the effective aspect ratio for power vias while maintaining multiple power planes for high current capacity
Solution Approach 2:
The patent applies different via diameter specifications locally: larger diameters for power vias traversing thick PCB sections to reduce aspect ratio and improve manufacturability, and smaller diameters for signal vias in thinner sections. This local differentiation enables multiple power planes without uniformly increasing manufacturing difficulty across the entire PCB
Data Source
AI summary
According to embodiments of the present disclosure, a printed circuit and manufacturing method thereof are provided. The printed circuit board comprises: a signal plane portion comprising a plurality of metal layers for transmitting a signal; a power plane portion overlaid with the signal plane portion through a connection layer and comprising a plurality of metal layers for providing power; a plurality of power vias each extending from a surface of the signal plane portion facing away from the power plane portion, through the signal plane portion, the connection layer, and the power plane portion, to a surface of the power plane portion facing away from the signal plane portion; and a plurality of signal vias each extending from a surface of the signal plane portion facing away from the power plane portion into the signal plane portion and not into the power plane portion.