Asymmetric PCB Layer Stack for Thin Board Warpage Control
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Solution Overview
Problem
Warpage issues in circuit boards during manufacturing processes, particularly in thinner designs, lead to reliability problems and hinder automated processes due to differences in thermal expansion coefficients and modulus of elasticity between insulating and metal layers.
Innovation Solution
A circuit board design with asymmetric thicknesses and thermal expansion coefficients in its substrate layers, specifically adjusting the thickness of outermost circuit pattern and protective layers, to minimize warpage and maintain flatness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the circuit board is made thinner to meet product miniaturization requirements, then the size and weight of the circuit board are reduced, but warpage occurs during manufacturing due to differences in thermal expansion coefficients and modulus of elasticity between insulating and metal layers
Solution Approach 1:
The patent applies asymmetry by making the first outermost circuit pattern layer have a greater thickness than the first inner circuit pattern layer and the second inner circuit pattern layer. This asymmetric thickness distribution compensates for the differential thermal expansion between metal and insulating layers, balancing the internal stresses and preventing warpage in thin circuit boards during manufacturing processes.
2Reliability
If the thickness of circuit pattern layers is increased to improve warpage resistance, then warpage is reduced, but the overall circuit board thickness increases
Solution Approach 1:
The patent applies local quality by selectively increasing the thickness of only the first outermost circuit pattern layer, while keeping the inner circuit pattern layers at standard thicknesses. This localized thickness enhancement provides warpage resistance where most needed (at the outermost layer exposed to thermal stress) without proportionally increasing the overall circuit board thickness.
3Productivity
If automated manufacturing processes are used to improve productivity, then production efficiency increases, but warpage during manufacturing causes automated processes such as strip test and assembly to fail
Solution Approach 1:
The patent applies preliminary anti-action by designing the circuit board with asymmetric circuit pattern layer thicknesses before manufacturing to preemptively counteract warpage forces that will occur during automated manufacturing processes. This pre-engineered thickness compensation ensures the board remains flat enough to accommodate automated strip testing and assembly processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly reduces warpage, enhancing physical and electrical reliability by maintaining flatness during manufacturing, thus improving the accuracy of processes like via hole formation and assembly.
Implementation Method 1
The causes of warpage are various, such as the difference in the coefficient of thermal expansion (CTE) and the difference in the modulus of elasticity between the insulating material and the metal circuit.
Data Source
AI summary
A circuit board according to an embodiment includes a first substrate layer; a second substrate layer disposed on the first substrate layer; and a third substrate layer disposed under the first substrate layer; wherein the second substrate layer includes: a first inner circuit pattern layer disposed on the first substrate layer; and a first outermost circuit pattern layer disposed on the first inner circuit pattern layer; wherein the third substrate layer includes: a second inner circuit pattern layer disposed under the first substrate layer; and a second outermost circuit pattern layer disposed under the second inner circuit pattern layer; wherein a thickness of the first outermost circuit pattern layer is greater than a thickness of each of the first inner circuit pattern layer and the second inner circuit pattern layer.