Asymmetric Printed Wiring Board Warping Control
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Solution Overview
Problem
Printed wiring boards face challenges in mounting IC chips due to warping issues during the reflow process, particularly with thinner or larger IC chips, where the thermal expansion coefficients of the IC chip and the board differ, leading to connection failures and delamination.
Innovation Solution
The printed wiring board design incorporates a core substrate with a first and second buildup layer, where the thermal expansion coefficient of the uppermost interlayer resin insulation layer is set lower than that of the lowermost interlayer resin insulation layer, achieved by varying the amount of inorganic particles and resin, to align the warping direction of the board with the IC chip, ensuring proper alignment and connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thermal expansion coefficients of the IC chip and the board are different, then the IC chip can be mounted on the board, but warping occurs during the reflow process leading to connection failures and delamination
Solution Approach 1:
The patent applies local quality by creating asymmetric thermal expansion characteristics in different regions of the printed wiring board. Specifically, the uppermost interlayer resin insulation layer is designed with a lower thermal expansion coefficient than the lowermost interlayer resin insulation layer. This localized differentiation in material properties allows the board to warp in a controlled direction that matches the IC chip's warping behavior during reflow, thereby maintaining connection reliability despite thermal expansion mismatches.
Solution Approach 2:
The patent employs parameter changes by modifying the thermal expansion coefficients of specific layers within the board structure. The uppermost interlayer resin insulation layer is formulated to have a thermal expansion coefficient of 50 ppm/K or lower, while the lowermost layer has a higher coefficient. This parameter differentiation enables the board to accommodate thermal stress during reflow processing and prevents delamination and connection failures.
2Reliability
If the uppermost interlayer resin insulation layer has a lower thermal expansion coefficient than the lowermost layer, then warping direction aligns with IC chip improving mounting yield, but the structure becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the interlayer resin insulation structure into distinct upper and lower portions with different thermal expansion coefficients. The uppermost interlayer resin insulation layer is separated from the lowermost layer, each with specifically controlled material properties. This segmentation allows independent optimization of thermal expansion characteristics to match IC chip warping behavior while maintaining a manageable layered structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the mounting yield of IC chips by aligning the warping direction of the board with the chip, improving connection reliability and reducing the likelihood of cracks in the interlayer resin insulation layers, even under high temperatures.
Implementation Method 1
the outermost interlayer resin insulation layer of the first buildup layer has a thermal expansion coefficient which is set lower than a thermal expansion coefficient of the outermost interlayer resin insulation layer of the second buildup layer
Data Source
AI summary
A printed wiring board includes a core substrate, an electronic component accommodated in the substrate, a first buildup layer laminated on first surface of the substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the first buildup layer, and a second buildup layer laminated on second surface of the substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the second buildup layer. The outermost interlayer resin insulation layer of the first buildup layer has thermal expansion coefficient which is set lower than thermal expansion coefficient of the outermost interlayer resin insulation layer of the second buildup layer.