Asymmetric Memory Pillar for Source Line Connection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor storage devices face challenges in manufacturing due to complex connection structures between memory pillars and source lines, particularly in highly stacked configurations, which can lead to decreased manufacturability and electrical characteristics.

Innovation Solution

The semiconductor storage device incorporates a multi-layered body with alternately stacked gate electrode layers and insulating layers, a pillar with an insulating core, channel layer, and memory film, and a source line positioned between the multi-layered body and the substrate, where the pillar's first end has a wider width than its second end, facilitating easier formation of the connection structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a highly stacked multi-layered body configuration is used to increase storage capacity, then the device density and capacity are improved, but the connection structure between memory pillars and source lines becomes more complex and difficult to manufacture

Engineering Contradiction:
Improvestorage capacityVSAvoidmanufacturability
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The memory pillar is designed with an asymmetric tapered structure where the first end (bottom) has a larger cross-sectional area than the second end (top). This asymmetric geometry simplifies the connection process with the source line at the wider first end, while maintaining the required storage functionality in the stacked configuration.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent transitions from a conventional planar connection approach to a vertical three-dimensional connection architecture. The memory pillar extends vertically through the multi-layered body, connecting the source line at the bottom to the channel layer at the top, utilizing the vertical dimension to simplify connection complexity in highly stacked devices.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If a highly stacked multi-layered body configuration is used to increase storage capacity, then the device density and capacity are improved, but the electrical characteristics and connectivity are degraded

Engineering Contradiction:
Improvestorage capacityVSAvoidelectrical characteristics
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The asymmetric tapered structure of the memory pillar, with a larger cross-sectional area at the first end, provides improved electrical contact with the source line. This geometric configuration reduces contact resistance and enhances connectivity, ensuring reliable electrical characteristics even in highly stacked configurations with many layers.

Inventive Principle:
Principle #4Asymmetry

3Ease of manufacture

If a conventional uniform pillar structure is used, then the manufacturing process is simpler, but the connection structure between memory pillar and source line becomes complex in highly stacked devices

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidconnection structure complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

By making the memory pillar asymmetric with a tapered structure, the patent simplifies the connection structure at the critical interface with the source line. The larger cross-sectional area at the first end provides a broader contact area, reducing the complexity of forming reliable connections in highly stacked devices compared to uniform pillar structures.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The memory pillar structure is designed in advance with a pre-formed tapered geometry that anticipates the connection requirements. This preliminary structural design facilitates easier and more reliable connection formation with the source line before the actual connection process occurs, reducing on-the-fly manufacturing complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250191618A1Semiconductor storage device and method of manufacturing semiconductor storage device
Publication Date: 2025.06.12 KIOXIA CORP
  • US20250191618A1 patent drawing
  • US20250191618A1 patent drawing
  • US20250191618A1 patent drawing

AI summary

A semiconductor storage device according to an embodiment includes a substrate, a transistor, a multi-layered body, a pillar, and a source line. The transistor is on the substrate. The multi-layered body includes a plurality of gate electrode layers and a plurality of insulating layers alternately stacked one by one in a first direction. The pillar includes an insulating core, a channel layer, and a memory film. The source line is between the multi-layered body and the substrate. The source line extends at least in a second direction. The pillar has a first end and a second end. The first end is in contact with the source line. The second end is on a side opposite to the first end in the first direction. A width of the first end in the second direction is larger than a width of the second end in the second direction.