Asymmetric Pixel Layout for Display Device Aperture Ratio
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Solution Overview
Problem
Contemporary liquid crystal displays (LCDs) face challenges in achieving high resolution and wide viewing angles due to the short spacing between data lines, which results in reduced aperture ratio and transmittance as the thin film transistors and contact holes are not aligned, leading to suboptimal performance.
Innovation Solution
The display device incorporates a design with data lines spaced apart by different distances, featuring thin film transistors aligned with contact holes and pixel electrodes of varying widths, along with a common electrode overlapping the pixel electrode with an insulating layer, to enhance alignment and improve aperture ratio and transmittance, while maintaining high resolution and wide viewing angles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If data lines are spaced closely together to increase pixel density, then resolution is improved, but aperture ratio and transmittance deteriorate due to misalignment of thin film transistors and contact holes
Solution Approach 1:
The patent applies local quality by creating asymmetric pixel areas where the first edge portion adjacent to one gate line has a greater length than the second edge portion adjacent to another gate line. This local asymmetry allows thin film transistors to be positioned at the first edge portion where there is sufficient space for proper alignment with contact holes, while maintaining close spacing of data lines elsewhere to achieve high resolution.
Solution Approach 2:
The patent employs asymmetry by designing pixel areas with non-uniform dimensions along the gate line direction. Specifically, the first edge portion of each pixel area has a greater length than the second edge portion, creating an asymmetric layout that provides adequate space for thin film transistor placement and alignment without requiring increased distance between data lines.
2Measurement precision
If data lines are spaced closely together to increase pixel density, then resolution is improved, but transmittance deteriorates due to reduced space for transparent conductive layers
Solution Approach 1:
The patent applies local quality by creating asymmetric pixel areas where the first edge portion adjacent to one gate line has a greater length than the second edge portion adjacent to another gate line. This local asymmetry allows thin film transistors to be positioned at the first edge portion where there is sufficient space for proper alignment with contact holes, while maintaining close spacing of data lines elsewhere to achieve high resolution.
Solution Approach 2:
The patent resolves the spacing conflict by utilizing the gate line direction (another dimension) to provide alignment space. Instead of requiring increased spacing between data lines in the column direction, the invention uses the asymmetric first edge portion extending along the gate line direction to accommodate thin film transistors and their alignment features, thereby maintaining high resolution while improving transmittance.
Data Source
AI summary
A display device includes a first substrate; a plurality of gate lines arranged in a row direction on the first substrate; a plurality of data lines arranged in a column direction intersecting the row direction; and a plurality of pixels formed in a plurality of pixel areas defined by the gate and data lines, the plurality of pixels comprising at least a first pixel and a second pixel respectively disposed in a first pixel area and a second pixel area that are immediately adjacent to each other. Each of the first and second pixels comprises a thin film transistor electrically connected to the gate and data lines, and a pixel electrode electrically connected to the thin film transistor. The data lines are disposed-apart by different distances from each other in the column direction. Each of the first and second pixel areas comprises a first edge portion adjacent to one of the gate lines and a second edge portion adjacent to another of the gate lines, a length of the first edge portion being greater than a length of the second edge portion. The thin film transistor is disposed at the first edge portion of the first and second pixel areas.