Asymmetric Plasma Barrier Layer for 3D NAND Landing Pads
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Solution Overview
Problem
In three-dimensional vertical NAND (3D VNAND) devices, the formation of via contact holes through dry etching can lead to electrical short circuits due to excessive etching, connecting the via contact hole to multiple conductive layers, which risks a short circuit when driving semiconductor devices.
Innovation Solution
A substrate processing method that selectively deposits a landing pad on a stepped structure without a separate photolithography process, ensuring uniform thickness across each step, using an asymmetric plasma process to densify the barrier layer on horizontal surfaces and etch it on vertical surfaces, preventing excessive etching and maintaining uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dry etching is used to form via contact holes, then the via contact holes can be formed efficiently, but excessive etching may occur connecting the via contact hole to multiple conductive layers, risking electrical short circuits
Solution Approach 1:
A barrier layer is deposited on the stepped structure before via contact hole formation. This barrier layer acts as a protective layer that prevents excessive etching from reaching and connecting multiple conductive layers, thereby eliminating the short circuit risk while maintaining efficient via contact hole formation through dry etching.
Solution Approach 2:
The barrier layer serves as an intermediary protective layer between the etching process and the conductive layers. It mediates the etching action, allowing controlled removal of material for via contact hole formation while preventing uncontrolled etching that would connect multiple conductive layers and cause short circuits.
2Manufacturing precision
If a separate photolithography process is performed to deposit landing pad, then precise positioning can be achieved, but the process complexity and manufacturing time increase
Solution Approach 1:
The invention extracts and eliminates the separate photolithography process from the manufacturing sequence. Instead of using photolithography for landing pad deposition, the method directly deposits the barrier layer on the stepped structure, which self-aligns to provide precise positioning without requiring additional photolithography steps, thereby reducing process complexity while maintaining precision.
Solution Approach 2:
The stepped structure itself serves as the positioning reference for barrier layer deposition. The barrier layer automatically aligns with the steps through conformal deposition, making the structure self-aligning and eliminating the need for external photolithography guidance, thus simplifying the manufacturing process while maintaining precision.
3Quantity of substance
If the number of stack structures in VNAND device increases, then device capacity improves, but maintaining uniform barrier layer thickness on each step becomes more difficult
Solution Approach 1:
The invention employs atomic layer deposition (ALD) which provides superior conformal coverage and thickness control compared to conventional deposition methods. ALD processes can maintain uniform film thickness even on complex three-dimensional stepped structures with multiple levels, ensuring consistent barrier layer thickness across all steps regardless of the increased number of stack structures, thereby maintaining manufacturing precision while enabling higher device capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the risk of short circuits by maintaining uniform barrier layer thickness across each step, preventing the via contact hole from connecting to another landing pad, thus ensuring reliable semiconductor device operation.
Implementation Method 1
an asymmetric plasma process to densify the barrier layer on horizontal surfaces
Implementation Method 2
The asymmetric plasma process may include a process of bombarding the barrier layer with ions in a unidirectional manner
Implementation Method 3
depositing a barrier layer on the stepped structure
Implementation Method 4
depositing a barrier layer on the stepped structure
Implementation Method 5
isotropically etching the barrier layer to form a barrier layer having a width narrower than a width of the mask layer
Data Source
AI summary
Provided is a substrate processing method that may prevent the non-uniformity of the thickness of landing pads deposited on each step in a vertical NAND device having a stepped structure. The substrate processing method includes stacking, a plurality of times, a stack structure including an insulating layer and a sacrificial layer and etching the stack structure to form a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface. The method also includes forming a barrier layer on the stepped structure, forming a mask layer on the barrier layer and exposing at least a portion of the barrier layer by etching at least a portion of the mask layer with a first etching solution The method further includes etching the exposed barrier layer with a second etching solution and etching the mask layer with a third etching solution.