Asymmetric Protective Layer for Spacer Profile Control
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Solution Overview
Problem
In semiconductor manufacturing, the shrinking critical dimensions and complex patterning processes lead to defects such as deformed profiles and height loss, affecting critical dimension control and feature transfer in multi-patterning techniques, resulting in early device failure.
Innovation Solution
The method involves forming and patterning a spacer layer using a protective layer and polymer layer deposition process, allowing different regions of the spacer layer to be etched at different rates or orders, with the protective layer primarily formed on the top surface to maintain desired profiles and dimensions during the patterning process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional optical lithography is used for patterning, then the manufacturing process is simple, but the critical dimension control deteriorates at 20nm node and below
Solution Approach 1:
The patterning process is divided into multiple sequential steps including forming mandrels, depositing spacer layers, selective etching, and multiple deposition cycles. This segmentation enables precise critical dimension control at 20nm node by breaking down the complex patterning into controllable stages, each optimizing specific geometric parameters
Solution Approach 2:
Protective layers are deposited on mandrel structures before the main etching process. This preliminary action protects specific regions during selective etching, enabling precise pattern formation while maintaining critical dimension accuracy in subsequent processing steps
2Manufacturing precision
If multi-patterning techniques are used to enhance feature density, then the manufacturing precision improves, but the process complexity and defect rate increase
Solution Approach 1:
Different regions of the spacer layer receive different treatments through selective protective layer deposition. The protective layer is applied predominantly on top surfaces rather than bottom surfaces, enabling localized protection during etching and preventing deformed profiles and height loss in critical regions
Solution Approach 2:
The process employs repeated cycles of protective layer formation and selective etching until the substrate surface is exposed. This continuous iterative approach maintains profile integrity throughout the multi-patterning process, preventing cumulative defects while achieving high feature density
3Shape
If the protective layer is formed predominantly on the top surface of the spacer layer, then the profile control improves, but the etching selectivity becomes more challenging
Solution Approach 1:
The protective layer deposition is designed to be asymmetric, forming predominantly on top surfaces of spacer layers rather than uniformly across all surfaces. This asymmetric deposition strategy optimizes profile control by protecting critical top regions while allowing controlled etching of bottom regions, achieving desired geometric shapes
Solution Approach 2:
The etching process uses periodic cycles of protective layer formation followed by selective etching operations. This periodic action allows repeated refinement of the spacer layer profile, achieving precise shape control while managing etching selectivity through multiple controlled stages
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control over the patterning process, reducing defects and ensuring accurate feature transfer, thereby improving the reliability and performance of semiconductor devices by maintaining desired profiles and dimensions.
Implementation Method 1
forming a protective layer on a spacer layer disposed on a structure disposed on a substrate, wherein the protective layer is formed predominately on a top surface of the spacer layer
Implementation Method 2
forming a protective layer on a spacer layer disposed on a structure disposed on a substrate
Implementation Method 3
forming a polymer layer on the substrate
Data Source
AI summary
Embodiments of the present disclosure provide methods and apparatus for forming and patterning a spacer layer for multi-patterning processes. In one embodiment, a method for patterning a spacer layer on a substrate includes forming a protective layer on a spacer layer disposed on a structure disposed on a substrate, wherein the protective layer is formed predominately on a top surface of the spacer layer, than a bottom surface of the spacer layer, etching the spacer layer from the bottom surface, forming a polymer layer on the substrate, etching a top portion of the polymer layer and a first portion the spacer layer located the top surface of the structure, and removing the structure from the substrate and leaving a second portion the spacer layer on the substrate.