Asymmetric Pull-Up Transistor for LCD Gate Driving Signal Stability
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Solution Overview
Problem
The instability of voltage in a-Si:H TFTs in gate driving signal output units of LCD devices leads to signal distortion and flickering, degrading picture quality due to the unsynchronized gate driving signals.
Innovation Solution
The implementation of an asymmetric structure in the pull-up transistor, with different overlap areas between the gate and source electrodes and the gate and drain electrodes, to create varying capacitance values, which helps in stabilizing the voltage and preventing abnormal gate driving signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a symmetric structure is used in the pull-up transistor with equal overlap areas between gate-source and gate-drain electrodes, then the manufacturing process is simple, but voltage instability occurs leading to signal distortion and flickering
Solution Approach 1:
The patent applies asymmetry by designing the pull-up transistor with different overlap areas between the gate electrode and source/drain electrodes. Specifically, the overlap area between the gate electrode and the drain electrode is made larger than the overlap area between the gate electrode and the source electrode. This asymmetric configuration creates different capacitance values (C1 and C2) that compensate for voltage instability in -Si:H TFTs, thereby preventing signal distortion and flickering without requiring additional components.
2Reliability
If an asymmetric structure with different overlap areas is implemented, then voltage stability is improved and signal distortion is minimized, but the device structure becomes more complex
Solution Approach 1:
The patent applies local quality by modifying only specific regions of the transistor structure - namely the overlap areas between the gate electrode and the source/drain electrodes. The rest of the transistor structure remains conventional and unchanged. This localized modification approach achieves voltage stabilization and signal synchronization while minimizing overall structural complexity and maintaining ease of manufacturing.
3Reliability
If additional components are added to stabilize voltage in gate driving signal output units, then signal distortion is reduced, but the integration size of the device increases
Solution Approach 1:
The patent merges the voltage stabilization function directly into the existing pull-up transistor structure by adjusting the overlap areas of the gate electrode with source and drain electrodes. This integration eliminates the need for separate stabilization components (such as additional capacitors or transistors) that would increase device area. The asymmetric overlap configuration itself provides the necessary voltage stability while maintaining compact integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes signal distortion and flickering by ensuring synchronized gate driving signals, thereby enhancing the picture quality and reducing the integration size of the device.
Implementation Method 1
The implementation of an asymmetric structure in the pull-up transistor, with different overlap areas between the gate and source electrodes and the gate and drain electrodes, to create varying capacitance values
Data Source
AI summary
An LCD device is disclosed, to minimize the signal distortion by decreasing the instability of voltage in a—Si:H TFT of a gate driving signal output unit, which includes a signal controller for outputting first and second control signals Q and /Q; a pull-up transistor between a clock signal terminal CLK and a gate driving signal output terminal for receiving the first control signal Q, the pull-up transistor having a first gate electrode, a first source electrode and a first drain electrode, wherein the pull-up transistor has an asymmetric structure in a first area of the first source electrode overlapped with the first gate electrode and a second area of the first drain electrode overlapped with the first gate electrode; and a pull-down transistor connected between the gate driving signal output terminal and a ground voltage terminal, wherein the pull-down transistor receives the second control signal.