Asymmetric Read-Write Sequencing for Interconnected Die Timing
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Solution Overview
Problem
Interconnected die architectures in memory devices experience timing delays during data transfer, impacting the overall performance of read and write operations.
Innovation Solution
Implementing an asymmetric read-write sequence that differs the order of data access between interface and linked dies, minimizing the impact of timing delays associated with the interconnected die architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If interconnected die architecture is used to increase memory capacity, then memory capacity is improved, but timing delay increases
Solution Approach 1:
The patent applies preliminary action by performing write operations to the linked die before read operations. The write sequence is designed to complete data transfer to the linked die in advance, so that when read operations are initiated, the data is already positioned and ready for retrieval, thereby reducing the timing delay penalty associated with interconnected die architecture.
Solution Approach 2:
The patent implements dynamic operation sequences that adapt to the specific architecture of interconnected dies. The memory controller dynamically adjusts the ordering and timing of write and read operations based on which die (interface or linked) is accessed, optimizing performance for different access patterns and reducing overall timing delays.
2Productivity
If data transfer between interface die and linked die is increased, then memory bandwidth is improved, but timing delay penalty increases
Solution Approach 1:
The patent ensures continuity of useful action by maintaining overlapping write and read operations across the interconnected dies. The asymmetric sequences allow data to be continuously transferred between the interface die and linked die without idle waiting periods, keeping the data transfer pipeline full and maximizing memory bandwidth while managing timing delays through efficient scheduling.
Data Source
AI summary
Apparatuses and techniques for implementing an asymmetric read-write sequence for interconnected dies are described. The asymmetric read-write sequence refers to an asymmetric die-access sequence for read versus write operations. The “asymmetric” term refers to a difference in an order in which data is written to or read from interface and linked dies of the interconnected die architecture. The orders for the read and write operations can be chosen such that a delay associated with transferring data between the interconnected dies occurs as data passes between the interface die and a memory controller. With asymmetric read-write burst sequences, overall timing of the read and write operations of a memory device may be impacted less, if at all, by a timing delay associated with the interconnected die architecture.