Asymmetric Redistribution Layer for Semiconductor Alignment
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face challenges in forming a redistribution layer (RDL) over contact pads with high alignment tolerance, particularly due to the limitations in width and pitch that affect electrical characteristics and interconnect surface area.
Innovation Solution
A method is developed to form a second conductive layer over a substrate, where the width is less than the first conductive layer along one axis and greater along a perpendicular axis, allowing for improved alignment tolerance and electrical connectivity without compromising contact characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the RDL width is reduced to achieve smaller device footprint, then device size decreases, but alignment tolerance deteriorates
Solution Approach 1:
The RDL is designed with asymmetric width characteristics: narrower than the contact pad along the first axis (improving footprint) and wider than the contact pad along the second axis (improving alignment tolerance). This asymmetric geometry allows simultaneous optimization of both device size and manufacturing precision.
Solution Approach 2:
The solution transitions from considering only single-dimensional RDL width to utilizing two-dimensional width characteristics. By controlling width differently along two perpendicular axes, the invention achieves both reduced footprint and improved alignment tolerance through dimensional differentiation.
2Reliability
If the RDL width is reduced to improve electrical characteristics, then signal integrity improves, but interconnect surface area decreases
Solution Approach 1:
The RDL exhibits asymmetric width: narrower along the first axis (improving electrical characteristics by reducing parasitic effects) and wider along the second axis (maintaining sufficient interconnect surface area for mechanical strength and alignment tolerance).
3Productivity
If the RDL is made narrower to achieve higher device density, then more components fit on the device, but alignment precision during manufacturing worsens
Solution Approach 1:
The RDL is configured with asymmetric dimensions: narrow width along the first axis enables higher device density, while wide width along the second axis provides generous alignment precision margins during manufacturing processes.
Data Source
AI summary
A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.