Asymmetric Reed-Solomon Decoder for Low-Logic Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Reed-Solomon decoder implementations for high-speed networks are excessively logic-intensive due to the requirement for numerous finite-field dividers and adaptive look-up tables, leading to high costs and power consumption, while they often provide error correction capabilities beyond what is needed for low error rates in modern networks.
Innovation Solution
The implementation of an asymmetric Reed-Solomon decoder that processes codewords with fewer check symbols, reducing the number of finite-field dividers and adaptive look-up tables required, by using syndrome computation, error locator polynomial, and error evaluator polynomial circuits to produce error values for data recovery, and employing a pipelined architecture with parallel stages to correct errors efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full-capability Reed-Solomon decoder is implemented to correct up to t erroneous symbols, then error correction capability is improved, but decoder complexity and logic circuitry increase significantly
Solution Approach 1:
The patent applies asymmetry by implementing a decoder that handles only a subset of error correction cases (e.g., correcting only 1 error instead of up to t errors). The syndrome computation and error correction logic are designed asymmetrically to process only the necessary check symbols for the actual error rate, rather than symmetrically handling all possible error combinations up to the maximum correction capability.
Solution Approach 2:
The patent extracts and removes unnecessary decoder components from the full-capability Reed-Solomon decoder. Specifically, it eliminates finite-field dividers and adaptive look-up tables that are required for high error correction capabilities but are not needed when operating at low error rates, thereby simplifying the decoder while maintaining adequate performance.
2Reliability
If the number of finite-field dividers is increased to handle longer codeword lengths, then error correction capability is improved, but decoder cost and power consumption increase
Solution Approach 1:
The patent removes finite-field dividers from the decoder implementation, replacing them with alternative computational approaches that consume less power. The syndrome computation and error correction are performed using simplified arithmetic operations that avoid the high power consumption associated with finite-field division, particularly for longer codeword lengths.
3Productivity
If pipelining is implemented to achieve high decoding output rates, then productivity is improved, but device complexity increases due to duplicative circuitry
Solution Approach 1:
The patent segments the decoding process into distinct stages (syndrome computation, error location identification, error value calculation, and codeword correction) that can be processed in parallel or pipelined fashion. Each stage operates independently with well-defined interfaces, allowing for efficient throughput optimization without requiring extensive duplicative circuitry across pipeline stages.
Data Source
AI summary
In an arrangement of the disclosed systems, devices, and methods, a codeword encoded with a first number of check symbols is received and asymmetrically processed according to a second number of check symbols, where the second number of check symbols is less than the first number of check symbols, to produce an error locator polynomial and an error evaluator polynomial. A derivative of the error locator polynomial is produced by outputting a first polynomial term and a second polynomial term, wherein the second polynomial term is a constant. The derivative of the error locator polynomial is produced using a variable finite-field multiplier and without use of a divider.