Asymmetric Select Gate Transistor for NAND Flash Reliability

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Solution Overview

Problem

NAND type flash memory devices require high driving power and reliability for select gate switch transistors, especially during data erasing operations, where high voltages are applied, and existing structures face challenges in balancing parasitic resistance and surface voltage resistance.

Innovation Solution

The implementation of a select gate switch transistor with a DDD structure for one source/drain region and an LDD structure for the other, optimizing impurity layers to reduce parasitic resistance and enhance surface voltage resistance, ensuring high drive power and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a select gate switch transistor is designed with high driving power to charge and discharge select gate lines, then the memory device can operate faster, but the transistor consumes more energy and generates more heat

Engineering Contradiction:

Improvecharging and discharging speed of select gate linesVSAvoidenergy consumption of select gate switch transistor

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent applies different impurity concentration profiles to different regions of the source/drain structure. The first source/drain region has a different impurity concentration distribution compared to the second source/drain region, allowing each region to be optimized for its specific function - one for high current drive and the other for low parasitic resistance, thus resolving the contradiction between speed and energy consumption

Inventive Principle:

Principle #3Local quality

2Productivity

If high voltage is applied to source/drain regions during erasing operation, then data can be erased from memory cells, but the select gate switch transistor experiences increased stress and reduced reliability

Engineering Contradiction:

Improvedata erasing capabilityVSAvoidreliability of select gate switch transistor

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent creates asymmetric source/drain regions with different impurity concentration profiles. The first source/drain region is designed with higher impurity concentration near the surface to withstand high voltage stress during erasing operations, while the second source/drain region has lower parasitic resistance. This local differentiation allows the transistor to maintain reliability under high voltage while preserving erasing functionality

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent pre-structures the source/drain regions with optimized impurity concentration profiles before the high voltage erasing operation occurs. The first source/drain region is prepared with higher impurity concentration to cushion against the high voltage stress, preventing damage before it occurs. This beforehand preparation ensures the transistor can withstand the erasing process without degradation

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Ease of manufacture

If the source/drain structure uses a single uniform impurity concentration, then the manufacturing process is simpler, but the parasitic resistance cannot be sufficiently reduced

Engineering Contradiction:

Improvesimplicity of source/drain structure fabricationVSAvoidparasitic resistance of source/drain regions

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent divides the source/drain structure into two distinct regions - a first source/drain region and a second source/drain region - each with different impurity concentration profiles. This segmentation allows independent optimization of each region's electrical properties, reducing overall parasitic resistance while maintaining manufacturing feasibility through sequential processing steps

Inventive Principle:

Principle #1Segmentation

4Stability of the object's composition

If both source/drain regions have the same impurity concentration profile, then the device symmetry is maintained, but the surface voltage resistance cannot be optimized for high voltage operation

Engineering Contradiction:

Improvesymmetry of source/drain structureVSAvoidsurface voltage resistance during erasing

Core Design Contradiction:

Stability of the object's compositionVSReliability

Solution Approach 1:

The patent intentionally introduces asymmetry in the impurity concentration profiles of the two source/drain regions. The first source/drain region has a different impurity concentration distribution compared to the second source/drain region, allowing one region to be specifically optimized for withstanding high voltage stress during erasing operations. This controlled asymmetry resolves the contradiction by prioritizing electrical performance over structural symmetry

Inventive Principle:

Principle #4Asymmetry

Data Source

PatentUS8569847B2Nonvolatile semiconductor memory device

Publication Date: 2013.10.29 KIOXIA CORP

AI summary

A nonvolatile semiconductor memory device in one embodiment includes a select gate switch transistor having a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and first and second source/drain regions provided in the semiconductor substrate so as to face each other across the gate electrode. The first source/drain region includes a first n-type impurity layer and a second n-type impurity layer which has a higher impurity concentration and has a shallower depth than the first n-type impurity layer. The second source/drain region has a third n-type impurity layer which has a lower impurity concentration and has a shallower depth than the first n-type impurity layer and a fourth n-type impurity layer which has a higher impurity concentration and has a deeper depth than the third n-type impurity layer.