Asymmetric Semiconductor Connectors for Fine Pitch Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packaging methods face challenges in forming reliable connectors with a flat surface to prevent underdevelopment during lithography processes, particularly in achieving a wider solder bridge joint formation process window and ensuring fine pitch interconnects.
Innovation Solution
The method involves forming connectors using plating processes over connector mounting regions with a substantially flat surface, where the connectors are wider at the bottom than at the top, and utilizing a multi-layer metal structure with a seed layer and photoresist layers to ensure accurate formation and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connectors are formed using conventional plating processes, then connectors can be created on semiconductor devices, but underdevelopment of photoresists occurs during lithography processes
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer before the plating process to create a substantially flat surface on the connector mounting region. This pre-preparation prevents underdevelopment of photoresists during subsequent lithography processes, as the flat surface ensures uniform photoresist coating and development.
Solution Approach 2:
The patent changes the surface topology parameter of the connector mounting region from non-planar to substantially flat by introducing a planarization layer. This parameter change (surface flatness) directly prevents photoresist underdevelopment while maintaining the connector's functional dimensions.
2Productivity
If connectors are formed with conventional dimensions, then standard interconnects are created, but the solder bridge joint formation process window is limited
Solution Approach 1:
The patent applies asymmetry by making the connector width at the bottom (first width) greater than the connector width at the top (second width). This asymmetric geometry provides a wider solder bridge joint formation process window at the base while maintaining appropriate top dimensions for fine pitch interconnects, thereby improving both productivity and reliability.
Solution Approach 2:
The patent applies local quality by having different width dimensions at different locations of the connector. The wider bottom portion provides enhanced solder bridge formation capability, while the narrower top portion maintains fine pitch interconnect requirements, optimizing local functions at different connector regions.
3Ease of manufacture
If photoresist layers are applied over non-planar surfaces, then connectors can be formed, but underdevelopment occurs during lithography processes
Solution Approach 1:
The patent applies preliminary action by creating a planarization layer before applying photoresist, establishing a substantially flat surface that enables accurate photoresist patterning without underdevelopment issues while still allowing connector formation.
4Productivity
If fine pitch interconnects are implemented, then higher integration density is achieved, but bonding shift issues increase
Solution Approach 1:
The patent applies asymmetry with the wider bottom connector portion providing enhanced bonding stability and reduced bonding shift issues, while the narrower top portion enables fine pitch interconnects for high integration density.
Solution Approach 2:
The patent applies local quality by optimizing different connector regions for different functions: the wider bottom region provides bonding stability, while the narrower top region enables fine pitch interconnects, thereby simultaneously achieving high integration density and bonding reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents underdevelopment of photoresists, enhances the reliability of connectors, and provides a wider solder bridge joint formation process window, improving the fine pitch interconnects and reducing bonding shift issues.
Implementation Method 1
connectors are formed using plating processes over connector mounting regions
Data Source
AI summary
Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.