Asymmetric Semiconductor Device Isolation for Low On-Resistance
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Solution Overview
Problem
High voltage transistors with a LOCOS offset type structure have a longer gate-source distance due to smaller offset diffusion layers on the drain side, leading to higher On-resistance and lower Off-breakdown voltage.
Innovation Solution
A semiconductor device structure with a lowly doped region, channel region, and isolation insulating films where the first device isolation film is thicker than the second, allowing deeper dopant ion implantation and reducing the gate-source resistance, thereby lowering On-resistance and maintaining higher Off-breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of the offset diffusion layer in the drain side is made smaller than that in the source side, then the sustaining breakdown voltage is improved, but the gate-source distance becomes longer and the On-resistance becomes higher
Solution Approach 1:
The patent applies local quality by making the offset diffusion layer asymmetric: the drain side offset diffusion layer has a smaller size than the source side offset diffusion layer. This localized differentiation allows the drain region to achieve higher sustaining breakdown voltage while the source region maintains lower resistance, resolving the contradiction between reliability and harmful factors.
2Reliability
If the gate-source distance is increased, then the Off-breakdown voltage is improved, but the On-resistance becomes higher
Solution Approach 1:
The patent creates local quality differences in the offset diffusion layer sizes to independently control the gate-source distance characteristics. By making the drain side offset smaller and source side offset larger, the structure achieves adequate gate-source distance for Off-breakdown voltage while minimizing the impact on On-resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure reduces On-resistance and maintains higher Off-breakdown voltage by shortening the gate-source distance and optimizing dopant distribution, improving the performance of high voltage transistors.
Implementation Method 1
allowing deeper dopant ion implantation and reducing the gate-source resistance
Data Source
AI summary
A field-effect transistor (142) includes a lowly p-doped region 110 formed on a surface of a substrate (102), an n-doped drain region 112 and n-doped source region 114 arranged on a surface of the lowly p-doped region 110, and a device isolation insulating film 132 and device isolation insulating film 134. Here, the device isolation insulating film 132 is formed greater in film thickness than the device isolation insulating film 134; and in the n-doped source region 114, the peak concentration section having a highest dopant concentration is formed in a deeper position than in the n-doped drain region 112.