Asymmetric Semiconductor Package with Differential Lead Widths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor package designs face challenges in reducing the total footprint while accommodating different die sizes and current carrying requirements of integrated circuits, as symmetric allocation of die mounting area and lead sizes is not optimal for varying amplifier configurations like Doherty amplifiers.
Innovation Solution
The semiconductor package features asymmetric allocation of die mounting areas and lead sizes tailored to the specific requirements of each amplifier, with distinct chip mounting sections and lead widths corresponding to the dimensions and power requirements of the main and peaking amplifiers, allowing for efficient use of space and optimized current carrying capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If symmetric allocation of die mounting area and lead sizes is used, then manufacturing simplicity is maintained, but space efficiency deteriorates when accommodating different amplifier sizes
Solution Approach 1:
The patent applies asymmetry by allocating different mounting area sections and lead widths to accommodate amplifiers of different sizes. Specifically, the mounting area is divided into first and second sections with different dimensions, and lead widths are varied (first and second leads have smaller width than third and fourth leads) to match the specific requirements of each amplifier, thereby optimizing space utilization while maintaining manufacturability
Solution Approach 2:
The patent implements local quality by tailoring the mounting area and lead characteristics to the specific needs of each amplifier location. The first amplifier is accommodated in a first mounting section with specific area constraints, while the second amplifier uses a second mounting section with different dimensions. Lead widths are locally optimized with narrower leads for the first amplifier and wider leads for the second amplifier, matching their respective power and signal requirements
2Area of stationary object
If lead width is reduced to minimize package footprint, then area efficiency improves, but current carrying capacity deteriorates
Solution Approach 1:
The patent applies local quality by assigning different lead widths to different amplifier connections based on their current requirements. The first and second leads have a smaller width suitable for the first amplifier's current needs, while the third and fourth leads have a larger width to accommodate the second amplifier's higher current requirements. This localized optimization ensures adequate current carrying capacity for each connection while minimizing the overall package footprint
Data Source
AI summary
A semiconductor device package includes a solid metal base with a top surface and an electrically conductive chip mounting area on the top surface. First and second pairs of conductive leads are attached to the base and extend away from one another in opposite directions. First and second amplifiers are attached to the top surface and are electrically connected to the first and second pairs of leads. The first pair is separated from the second pair by a horizontal gap between inner edge sides of the leads. A reference line in the horizontal gap that extends perpendicular to edges of the base divides the chip mounting area into first and second chip mounting sections. An area of the first chip mounting section is smaller than an area of the second chip mounting section. The first and second leads have a smaller width than the third and fourth leads.